{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,29]],"date-time":"2025-10-29T03:32:24Z","timestamp":1761708744457},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2012,5,1]],"date-time":"2012-05-01T00:00:00Z","timestamp":1335830400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2012,5]]},"DOI":"10.1109\/tcsi.2012.2189042","type":"journal-article","created":{"date-parts":[[2012,4,11]],"date-time":"2012-04-11T19:42:26Z","timestamp":1334173346000},"page":"926-937","source":"Crossref","is-referenced-by-count":25,"title":["Quantization Noise Suppression in Fractional-$N$ PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider"],"prefix":"10.1109","volume":"59","author":[{"given":"Jing","family":"Jin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoming","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tingting","family":"Mo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianjun","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"crossref","first-page":"877","DOI":"10.1109\/TCSI.2009.2016180","article-title":"Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs","volume":"56","author":"lin","year":"2009","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref32","first-page":"681","article-title":"An 18 mW 90 to 770 MHz synthesizer with agile auto-tuning for digital TV-tuners","author":"marutani","year":"2006","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.920355"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2161163"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.800925"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"2500","DOI":"10.1109\/JSSC.2006.883325","article-title":"A quantization noise suppression technique for <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta\\Sigma$<\/tex><\/formula> fractional-N frequency synthesizers","volume":"41","author":"yang","year":"2006","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref11","first-page":"396","article-title":"A 975-to-1960 MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4\/4.5 prescaler for digital TV tuners","author":"lu","year":"2009","journal-title":"Proc ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937606"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1453","DOI":"10.1109\/4.871322","article-title":"A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta\\Sigma$<\/tex> <\/formula> modulator","volume":"35","author":"rhee","year":"2000","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857429"},{"key":"ref15","year":"0","journal-title":"GY\/T 220 1-2006 China Mobile Multimedia Broadcasting Part 1"},{"key":"ref16","first-page":"270","author":"razavi","year":"1998","journal-title":"RF Microelectronics"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.508200"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.848211"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1010166"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2103170"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831598"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2106351"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820858"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908763"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.885999"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884829"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2110390"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2022301"},{"key":"ref2","year":"1971","journal-title":"Frequency synthesizer"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"966","DOI":"10.1109\/JSSC.2006.870894","article-title":"A 1-MHZ bandwidth 3.6-GHz 0.18 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\hbox {m}}$<\/tex><\/formula> CMOS fractional-N synthesizer utilizing a hybrid PFD\/DAC structure for reduced broadband phase noise","volume":"41","author":"meninger","year":"2006","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"201","DOI":"10.1109\/FREQ.1969.199763","article-title":"digiphase synthesizer","author":"gillette","year":"1969","journal-title":"23rd Annual Symposium on Frequency Control"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"866","DOI":"10.1109\/JSSC.2003.811875","article-title":"A 2.4-GHz monolithic fractional-<formula formulatype=\"inline\"><tex Notation=\"TeX\">$N$<\/tex><\/formula> frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier","volume":"38","author":"shu","year":"2003","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"1039","DOI":"10.1109\/4.848214","article-title":"A family of low-power truly modular programmable dividers in standard 0.35 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\hbox {m}}$<\/tex><\/formula> CMOS technology","volume":"35","author":"vaucher","year":"2000","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"5027","DOI":"10.1109\/ISCAS.2005.1465763","article-title":"A new 5 GHz CMOS dual-modulus prescaler","volume":"5","author":"yu","year":"2005","journal-title":"Proc Int Symp Circuits Syst (ISCAS)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/92.285754"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2005.858978"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2016183"},{"key":"ref25","first-page":"332","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/6194305\/06176273.pdf?arnumber=6176273","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:54:10Z","timestamp":1633910050000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6176273\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5]]},"references-count":34,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2012.2189042","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,5]]}}}