{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,6,28]],"date-time":"2023-06-28T21:52:41Z","timestamp":1687989161724},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2012,8,1]],"date-time":"2012-08-01T00:00:00Z","timestamp":1343779200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2012,8]]},"DOI":"10.1109\/tcsi.2012.2206503","type":"journal-article","created":{"date-parts":[[2012,7,14]],"date-time":"2012-07-14T02:57:43Z","timestamp":1342234663000},"page":"1644-1655","source":"Crossref","is-referenced-by-count":3,"title":["An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example"],"prefix":"10.1109","volume":"59","author":[{"given":"Yu-Shun","family":"Wang","sequence":"first","affiliation":[]},{"given":"Min-Han","family":"Hsieh","sequence":"additional","affiliation":[]},{"given":"James Chien-Mo","family":"Li","sequence":"additional","affiliation":[]},{"given":"Charlie Chung-Ping","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2003.1214372"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"401","DOI":"10.1109\/DFTVS.2003.1250137","article-title":"Error detection in signed digit arithmetic circuit with parity checker","author":"cardarilli","year":"2003","journal-title":"Proc 18th IEEE Int Symp Defect Fault Tolerance VLSI Syst"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.800526"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676477"},{"key":"ref11","author":"wang","year":"2006","journal-title":"VLSI Test Principles and Architectures Design for Testability"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.904155"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055417"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1973.5009159"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2000.852887"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1987.6158699"},{"key":"ref17","first-page":"318","article-title":"Sub-500 ps 64b ALUs in <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$0.18~\\mu {\\rm m}$<\/tex><\/formula> SOI\/bulk CMOS: Design and scaling trends","author":"mathew","year":"2001","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref18","first-page":"1735","article-title":"A 240 ps 64 b carrylookahead adder in 90-nm CMOS","author":"kao","year":"2006","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","first-page":"210","article-title":"A sub-nanosecond <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$0.5~\\mu {\\rm m}~64~{\\rm b}$<\/tex><\/formula> adder design","author":"naffziger","year":"1996","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref28","first-page":"162","article-title":"A 4 GHz 300 mW 64 b integer execution ALU with dual supply voltages in 90 nm CMOS","volume":"519","author":"mathew","year":"2004","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","author":"ma","year":"1995","journal-title":"Testing BiCMOS and dynamic CMOS logic"},{"key":"ref27","first-page":"332","article-title":"Clock-delayed domino for adder and combinational logic design","author":"yee","year":"1996","journal-title":"Proc IEEE\/ACM Int Conf Comput Design"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295104"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1997.643907"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"2696","DOI":"10.1109\/TCSI.2007.910537","article-title":"Self-checking carry-select adder design based on two-rail encoding","volume":"54","author":"vasudevan","year":"2007","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref5","year":"1999","journal-title":"Domino scan architecture and domino scan flipflop for the testing of domino and hybrid CMOS circuit"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1999.762825"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.53577"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011103"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"242","DOI":"10.1145\/157485.164880","article-title":"an efficient partitioning strategy for pseudo-exhaustive testing","author":"srinivasan","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1232252"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822775"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676202"},{"key":"ref21","author":"sutherland","year":"1999","journal-title":"Logical Effort Designing Fast CMOS Circuits"},{"key":"ref24","year":"0","journal-title":"Semiconductor device with speed binning test circuit and test method thereof"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000248"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1993.470604"},{"key":"ref25","author":"weste","year":"2005","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/6248238\/06239623.pdf?arnumber=6239623","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:51:18Z","timestamp":1633909878000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6239623\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":32,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2012.2206503","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,8]]}}}