{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,21]],"date-time":"2025-06-21T11:26:51Z","timestamp":1750505211200},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2013,4,1]],"date-time":"2013-04-01T00:00:00Z","timestamp":1364774400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/tcsi.2012.2209302","type":"journal-article","created":{"date-parts":[[2012,10,16]],"date-time":"2012-10-16T20:40:27Z","timestamp":1350420027000},"page":"938-950","source":"Crossref","is-referenced-by-count":13,"title":["A Reconfigurable SIMT Processor for Mobile Ray Tracing With Contention Reduction in Shared Memory"],"prefix":"10.1109","volume":"60","author":[{"given":"Hong-Yun","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Young-Jun","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie-Hwan","family":"Oh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lee-Sup","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2038922"},{"key":"ref11","author":"pharr","year":"2004","journal-title":"Physically Based Rendering From Theory to Implementation"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/RT.2006.280210"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1198555.1198798"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1572769.1572792"},{"key":"ref15","year":"0","journal-title":"NVIDIA CUDA Documentation"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2171417"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1972.8647"},{"key":"ref18","author":"muchnick","year":"1997","journal-title":"Advanced Compiler Design and Implementation"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090858"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/RT.2006.280209"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.9"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373399"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.916616"},{"key":"ref8","first-page":"262","article-title":"A 9.7 mW AAC-decoding, 620 mW H.264 720 p 60 fps decoding, 8-core media processor with embedded forward-body-biasing and power-gating circuit in 65 nm CMOS technology","author":"nomura","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2002.800860"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2009.934113"},{"key":"ref9","year":"2007","journal-title":"Press Release NVIDIA Tesla GPU Computing Processor Ushers In the Era of Personal Supercomputing"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.160"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.45"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118127"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2000.824366"},{"key":"ref24","year":"0","journal-title":"FX Composer 2 5"},{"key":"ref23","year":"0","journal-title":"PBRT Physically Based Ray Tracing"},{"key":"ref26","first-page":"27","article-title":"SaarCOR: A hardware architecture for ray tracing","author":"schmittler","year":"2002","journal-title":"Proc Graphics hardware"},{"key":"ref25","article-title":"GPGPU-Sim: A performance simulator for massively multithreaded processor research","year":"2009","journal-title":"Tutorial of IEEE\/ACM MICRO-42"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/6486561\/06289395.pdf?arnumber=6289395","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:41:45Z","timestamp":1638218505000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6289395\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":27,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2012.2209302","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,4]]}}}