{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T18:55:44Z","timestamp":1771613744255,"version":"3.50.1"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/tcsi.2013.2264690","type":"journal-article","created":{"date-parts":[[2013,6,11]],"date-time":"2013-06-11T18:02:22Z","timestamp":1370973742000},"page":"146-159","source":"Crossref","is-referenced-by-count":3,"title":["HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning"],"prefix":"10.1109","volume":"61","author":[{"given":"Youngsoo","family":"Shin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Insup","family":"Shin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donkyu","family":"Baek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Duckhwan","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seungwhun","family":"Paik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","year":"2010","journal-title":"NanoSim User Guide"},{"key":"ref30","first-page":"582","article-title":"An integrated design flow for a via-configurable gate array","author":"ran","year":"2004","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1998.746320"},{"key":"ref11","first-page":"283","article-title":"Manufacturing challenges in double patterning lithography","author":"arnold","year":"2005","journal-title":"Proc Int Symp Semiconductor Manufacturing"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1117\/12.485282","article-title":"Mask cost for sub-100 nm technologies: Stopping a runaway?","author":"balasinski","year":"2003","journal-title":"Proc SPIE"},{"key":"ref13","year":"2011","journal-title":"Private Communication With National Nanofab Center in Korea"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366185"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378019"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2003.1249358"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1693229"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996624"},{"key":"ref19","year":"2008","journal-title":"Design Compiler User Guide"},{"key":"ref28","year":"0"},{"key":"ref4","author":"lapedus","year":"2008","journal-title":"Can the Industry Afford a 32 nm ?Mask-Set??"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/800158.805069"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1002\/9781119990413"},{"key":"ref6","first-page":"192","article-title":"Design automation for mask programmable fabrics","author":"shenoy","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref29","year":"0"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1117\/12.612856"},{"key":"ref7","year":"2010","journal-title":"Wafer Lithography Mask and Wafer Lithography Method Using the Same"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240929"},{"key":"ref9","year":"2002","journal-title":"Athena User's Manual"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722217"},{"key":"ref20","year":"2007","journal-title":"Soc Encounter User Guide"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1002\/nav.3800020109"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1287\/moor.4.3.233"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","article-title":"VPR: a new packing, placement and routing tool for FPGA research","author":"betz","year":"1997","journal-title":"Proc Int Workshop Field Programmable Logic Appl"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/0020-0190(87)90107-4"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1961.5219222"},{"key":"ref25","year":"0"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/6704325\/06529196.pdf?arnumber=6529196","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:32:00Z","timestamp":1642005120000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6529196\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":31,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2013.2264690","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,1]]}}}