{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T02:27:01Z","timestamp":1781836021171,"version":"3.54.5"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"ND EPSCoR"},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Beijing Municipal Natural Science Foundation"},{"name":"Ph.D. Programs Foundation of Ministry of Education of China"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/tcsi.2014.2298280","type":"journal-article","created":{"date-parts":[[2014,2,3]],"date-time":"2014-02-03T14:04:31Z","timestamp":1391436271000},"page":"1970-1983","source":"Crossref","is-referenced-by-count":11,"title":["Variation Aware Sleep Vector Selection in Dual &lt;formula formulatype=\"inline\"&gt;&lt;tex Notation=\"TeX\"&gt;${\\rm V}_{{{\\rm t}}}$&lt;\/tex&gt;&lt;\/formula&gt; Dynamic OR Circuits for Low Leakage Register File Design"],"prefix":"10.1109","volume":"61","author":[{"given":"Na","family":"Gong","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jinhui","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ramalingam","family":"Sridhar","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2025591"},{"key":"ref38","first-page":"31","article-title":"A comparative analysis of gate leakage and performance of high-K nanoscale CMOS logic gates","author":"mohanty","year":"2007","journal-title":"Proc ACM\/IEEE Int Workshop on Logic Synthesis"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2015455"},{"key":"ref32","year":"2009"},{"key":"ref31","year":"0","journal-title":"Predictive Technology Model (PTM)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2010.5784663"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413116"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.50"},{"key":"ref35","first-page":"93","article-title":"Managing process variation in intel's 45 nm CMOS technology","volume":"12","author":"kuhn","year":"2008","journal-title":"Intel Technol J"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1587\/elex.8.1406"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.876463"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2004.1260928"},{"key":"ref29","first-page":"225","article-title":"Using charge self-compensation domino full-adder with multiple supply and dual threshold voltage in 45 nm","author":"wang","year":"2009","journal-title":"Proc ULIS"},{"key":"ref2","year":"1999","journal-title":"AMD Athlon Processor Technical Brief"},{"key":"ref1","first-page":"1","article-title":"The microarchitecture of the pentium 4 processor","volume":"5","author":"hinton","year":"2001","journal-title":"Intel Technol J"},{"key":"ref20","year":"0","journal-title":"MOSIS Deep Design Rules"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.826198"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"1311","DOI":"10.1109\/TVLSI.2007.903947","article-title":"PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies","volume":"15","author":"liu","year":"2007","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref24","year":"2002","journal-title":"Intel E7500 Chipset Datasheet"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380803"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2008.01.028"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364650"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2167823"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2039684"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2037449"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.848210"},{"key":"ref13","first-page":"359","article-title":"PVT variations aware optimal sleep vector determination of dual <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm V}_{\\rm t}$<\/tex><\/formula> domino OR circuits","author":"gong","year":"2011","journal-title":"Proc SOCC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICECE.2006.355679"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1582710.1582714"},{"key":"ref16","author":"kanter","year":"2010","journal-title":"Intel's Sandy Bridge Microarchitecture"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/381677.381702"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1049\/el.2012.0039"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817515"},{"key":"ref4","first-page":"110","article-title":"A 9 GHz 65 nm intel pentium\ufffd 4 processor integer execution core","author":"wijeratne","year":"2006","journal-title":"Proc ISSCC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494029"},{"key":"ref6","first-page":"256","article-title":"A 4R2W register file for a 2.3 GHz wire-speed power? processor with double-pumped write operation","author":"ditlow","year":"2011","journal-title":"Proc ISSCC"},{"key":"ref5","first-page":"1785","article-title":"An 8.8 GHz 198 mW 16<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\, \\times \\,$<\/tex><\/formula>64b 1R\/1W variation-tolerant register file in 65 nm CMOS","author":"hsu","year":"2006","journal-title":"Proc ISSCC"},{"key":"ref8","first-page":"328","article-title":"A 320 mV-to-1.2 V on-die fine-grained reconfigurable fabric for DSP\/media accelerators in 32 nm CMOS","author":"agarwal","year":"2010","journal-title":"Proc ISSCC"},{"key":"ref7","first-page":"286","article-title":"A 45 nm CMOS 13-port 64-Word 41b fully associative content-addressable register file","author":"burda","year":"2010","journal-title":"Proc ISSCC"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2008502"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560334"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2007.10.001"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2057230"},{"key":"ref48","year":"0","journal-title":"Cacti5"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2008.4492731"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.850860"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.57"},{"key":"ref44","author":"do","year":"2007","journal-title":"Capturing Process-Voltage-Temperature (PVT) Variations in Architectural Static Power Modeling for SRAM Arrays"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796757"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/6842725\/06730965.pdf?arnumber=6730965","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:55:41Z","timestamp":1641988541000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6730965\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":49,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2014.2298280","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,7]]}}}