{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,14]],"date-time":"2026-03-14T19:00:42Z","timestamp":1773514842810,"version":"3.50.1"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2015]]},"DOI":"10.1109\/tcsi.2015.2500420","type":"journal-article","created":{"date-parts":[[2015,12,17]],"date-time":"2015-12-17T19:40:36Z","timestamp":1450381236000},"page":"1-12","source":"Crossref","is-referenced-by-count":12,"title":["A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb\/s"],"prefix":"10.1109","author":[{"given":"Il-Min","family":"Yi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Soo-Min","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seung-Jun","family":"Bae","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Young-Soo","family":"Sohn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jung-Hwan","family":"Choi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seong-Jin","family":"Jang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Byungsub","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jae-Yoon","family":"Sim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hong-June","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910807"},{"key":"ref11","first-page":"136","article-title":"Single-ended transceiver design techniques for 5.33 Gb\/s graphics applications","author":"partovi","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2262186"},{"key":"ref13","first-page":"193","article-title":"A 40 nm 7 Gb\/s\/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface","author":"bae","year":"2010","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014733"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.881207"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108120"},{"key":"ref17","first-page":"134","article-title":"A 19 Gb\/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45 nm SOI CMOS","author":"agarwal","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2028449"},{"key":"ref19","first-page":"262","article-title":"A 95 fJ\/b current-mode transceiver for 10 mm on-chip interconnect","author":"lee","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref4","first-page":"446","article-title":"A 15 Gb\/s 0.5 mW\/Gb\/s 2-tap DFE receiver with far-end crosstalk cancellation","author":"nazari","year":"2011","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031015"},{"key":"ref6","first-page":"306","article-title":"A 6.4-Gb\/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems","author":"kaviani","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref5","first-page":"636","article-title":"A 0.4-mW\/Gb\/s, 16-Gb\/s near-ground receiver front-end with replica transconductance termination calibration","author":"kaviani","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917522"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2075410"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658406"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908692"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2036761"},{"key":"ref20","first-page":"156","article-title":"A 47 <ref_formula><tex Notation=\"TeX\">$\\times$<\/tex> <\/ref_formula> 10 Gb\/s 1.4 mW\/(Gb\/s) parallel interface in 45 nm CMOS","author":"o'mahony","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2249812"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746260"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/7407434\/7358166.pdf?arnumber=7358166","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:48:17Z","timestamp":1642006097000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7358166\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/tcsi.2015.2500420","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015]]}}}