{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T15:33:42Z","timestamp":1772206422706,"version":"3.50.1"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Basic Science Research Program"},{"DOI":"10.13039\/501100002701","name":"Ministry of Education","doi-asserted-by":"publisher","award":["2010-0020163"],"award-info":[{"award-number":["2010-0020163"]}],"id":[{"id":"10.13039\/501100002701","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002701","name":"Ministry of Education","doi-asserted-by":"publisher","award":["2013R1A2A2A01015738"],"award-info":[{"award-number":["2013R1A2A2A01015738"]}],"id":[{"id":"10.13039\/501100002701","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tcsi.2016.2528480","type":"journal-article","created":{"date-parts":[[2016,3,15]],"date-time":"2016-03-15T14:16:50Z","timestamp":1458051410000},"page":"482-493","source":"Crossref","is-referenced-by-count":18,"title":["A 0.8-to-6.5 Gb\/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling"],"prefix":"10.1109","volume":"63","author":[{"given":"Kyongsu","family":"Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jae-yoon","family":"Sim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2429714"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108120"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047439"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2283853"},{"key":"ref14","article-title":"Clock-embedded source synchronous semiconductor transmitting and receiving apparatus and semiconductor system including same","author":"lee","year":"2015"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914290"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804340"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2254552"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2043012"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040116"},{"key":"ref4","first-page":"142","article-title":"A 52 MHz and 155 MHz clock-recovery PLL","author":"de vito","year":"0","journal-title":"IEEE Int Solid-State Circuit Conf Dig Tech Papers"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2296152"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1979.1094553"},{"key":"ref6","first-page":"144","article-title":"A 180-Mb\/s to 3.2-Gb\/s, continuous-rate, fast-locking CDR without using external reference clock","author":"hwang","year":"0","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.856577"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2168872"},{"key":"ref7","first-page":"184","article-title":"A 650 Mb\/s-to-8 Gb\/s referenceless CDR circuit with automatic acquisition of data rate","author":"lee","year":"0","journal-title":"IEEE Int Solid-State Circuit Conf Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831809"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2327291"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.173101"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2016701"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822774"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804339"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2007.901130"},{"key":"ref23","first-page":"978","article-title":"A 63 GHz low-noise active balun with broadband phase-correction technique in 90 nm CMOS","author":"chiang","year":"0","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/4.871320"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.862071"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/7454660\/7434014.pdf?arnumber=7434014","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:43:56Z","timestamp":1641987836000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7434014\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":27,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2016.2528480","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}