{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,3]],"date-time":"2025-06-03T06:04:05Z","timestamp":1748930645734,"version":"3.37.3"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2016,6,1]],"date-time":"2016-06-01T00:00:00Z","timestamp":1464739200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004359","name":"Swedish Research Council","doi-asserted-by":"publisher","award":["621-2011-4540"],"award-info":[{"award-number":["621-2011-4540"]}],"id":[{"id":"10.13039\/501100004359","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002394","name":"Swedish VINNOVA Industrial Excellence Centre (SoS)","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002394","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2016,6]]},"DOI":"10.1109\/tcsi.2016.2537931","type":"journal-article","created":{"date-parts":[[2016,4,28]],"date-time":"2016-04-28T21:02:09Z","timestamp":1461877329000},"page":"806-817","source":"Crossref","is-referenced-by-count":19,"title":["Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS"],"prefix":"10.1109","volume":"63","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1663-5599","authenticated-orcid":false,"given":"Oskar","family":"Andersson","sequence":"first","affiliation":[]},{"given":"Babak","family":"Mohammadi","sequence":"additional","affiliation":[]},{"given":"Pascal","family":"Meinerzhagen","sequence":"additional","affiliation":[]},{"given":"Andreas","family":"Burg","sequence":"additional","affiliation":[]},{"given":"Joachim Neves","family":"Rodrigues","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","first-page":"274","article-title":"Ultra-low power 12T dual port SRAM for hardware accelerators","author":"wang","year":"0","journal-title":"Proc Int SoC Design Conf"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/4.535411"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.882218"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2100834"},{"key":"ref36","first-page":"81","article-title":"Controlled placement of standard cell memory arrays for high density and low power in 28 nm FD-SOI","author":"teman","year":"0","journal-title":"Proc Asia and South Pacific Design Automation Conf"},{"key":"ref35","first-page":"1785","article-title":"An 8.8 GHz 198 mW 16 $\\times$ 64 b 1R\/1W variation tolerant register file in 65 nm CMOS","author":"hsu","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref34","first-page":"316","article-title":"A 200 mV to 1.2 V, 4.4 MHz to 6.3 GHz, 48 $\\times$ 42 b 1R\/1W programmable register file in 65 nm CMOS","author":"agarwal","year":"0","journal-title":"Proc 33rd Eur Solid-State Circuits Conf"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032493"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907996"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"ref13","first-page":"243","article-title":"A 35 fJ\/bit-access sub- ${V}_\\mathrm{T}$ memory using a dual-bit area-optimized standard-cell in 65 nm CMOS","author":"andersson","year":"0","journal-title":"Proc Eur Solid-State Circuits Conf"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168911"},{"key":"ref15","first-page":"321","article-title":"A 500 fW\/bit 14 fJ\/bit-access 4 kb standard-cell based sub- ${V}_\\mathrm{T}$ memory in 65 nm CMOS","author":"meinerzhagen","year":"0","journal-title":"Proc Eur Solid-State Circuits Conf"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2162159"},{"key":"ref17","first-page":"1","article-title":"Sizing of dual- ${V}_\\mathrm{T}$ gates for sub- ${V}_\\mathrm{T}$ circuits","author":"mohammadi","year":"0","journal-title":"IEEE Subthreshold Microelectronics Conf"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/92.748196"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/92.924061"},{"key":"ref28","first-page":"252","article-title":"A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS","author":"chang","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2220671"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2309692"},{"key":"ref3","first-page":"66","article-title":"A 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS","author":"jain","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2177004"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873215"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2221217"},{"key":"ref8","first-page":"313","article-title":"A 65 nm SRAM achieving 250 mV retention and 350 mV, 1 MHz, 55 fJ\/bit access energy, with bit-interleaved radiation soft error tolerance","author":"clerc","year":"0","journal-title":"Proc Eur Solid-State Circuits Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2198984"},{"key":"ref2","first-page":"154","article-title":"A 2.60 pJ\/Inst subthreshold sensor processor for optimal energy efficiency","author":"zhai","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891726"},{"key":"ref1","first-page":"292","article-title":"A 180 mV FFT processor using subthreshold circuit techniques","author":"wang","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/263272.263362"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2273844"},{"key":"ref21","first-page":"1","article-title":"Dual threshold voltage adder for robust sub-vt operation in 65 nm technology","author":"jagasivamani","year":"0","journal-title":"Proc IEEE SOI-3D-Subthreshold Microelectron Technol Unified Conf"},{"key":"ref24","first-page":"456","article-title":"A 210 mV 5 Mhz variation-resilient near-threshold JPEG encoder in 40 nm CMOS","author":"reynders","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2418151"},{"key":"ref26","first-page":"1","article-title":"A 0.28&#x2013;0.8 V 320 fW D-latch for sub-VT memories in 65-nm CMOS","author":"mohammadi","year":"0","journal-title":"IEEE Faible Tension Faible Consommation IEEE"},{"key":"ref25","first-page":"197","article-title":"Dual- ${V}_\\mathrm{T}$ 4 kb sub- ${V}_\\mathrm{T}$ memories with $<$ 1 pW\/bit leakage in 65 nm CMOS","author":"andersson","year":"0","journal-title":"Proc Eur Solid-State Circuits Conf"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/7514296\/07462238.pdf?arnumber=7462238","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:43:33Z","timestamp":1641987813000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7462238\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6]]},"references-count":36,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2016.2537931","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2016,6]]}}}