{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T12:04:38Z","timestamp":1740139478367,"version":"3.37.3"},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2017,6,1]],"date-time":"2017-06-01T00:00:00Z","timestamp":1496275200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100004358","name":"FLASH Design Team, Memory Division, Samsung Electronics Co., Ltd., South Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2017,6]]},"DOI":"10.1109\/tcsi.2017.2654270","type":"journal-article","created":{"date-parts":[[2017,1,26]],"date-time":"2017-01-26T20:40:59Z","timestamp":1485463259000},"page":"1444-1455","source":"Crossref","is-referenced-by-count":6,"title":["Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM"],"prefix":"10.1109","volume":"64","author":[{"given":"Junyoung","family":"Ko","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Younghwi","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jisu","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Younghoon","family":"Oh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H. K.","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0757-2581","authenticated-orcid":false,"given":"Seong-ook","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"474","article-title":"A 512kB embedded phase change memory with 416kB\/s write throughput at 100\n$\\mu \\text{A}$\n cell write current","author":"hanzawa","year":"2007","journal-title":"IEEE Int Solid-State Circuit Conf Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1063\/1.3653279"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908001"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2052640"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4419107"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.5120\/16731-5665"},{"article-title":"Determining cell-state in phase-change memory","year":"2014","author":"frey","key":"ref16"},{"key":"ref17","first-page":"1","article-title":"1D thickness scaling study of phase change material (Ge2Sb2Te5) using a pseudo 3-terminal device","author":"bae","year":"2009","journal-title":"IEDM Tech Dig"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.375969"},{"key":"ref19","first-page":"293","article-title":"A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance","author":"kim","year":"2011","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556227"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2452352"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131482"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223706"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2011.5873231"},{"article-title":"Nonvolatile memory device using variable resistive element and memory system having the same","year":"2014","author":"lee","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0439"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176872"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523240"},{"article-title":"Linear amplifier with transient current boost","year":"1989","author":"wright","key":"ref20"},{"key":"ref22","first-page":"1","article-title":"Drift-tolerant multilevel phase-change memory","author":"khwa","year":"2015","journal-title":"Proc IEEE Int Memory Workshop (IMW)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2220459"},{"key":"ref23","first-page":"737","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","author":"wu","year":"2009","journal-title":"Proc Design Autom Test Eur Conf Exhibit"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/7934110\/07835212.pdf?arnumber=7835212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:14:35Z","timestamp":1642004075000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7835212\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6]]},"references-count":23,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2017.2654270","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2017,6]]}}}