{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,31]],"date-time":"2025-05-31T05:07:19Z","timestamp":1748668039067,"version":"3.37.3"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2017,7,1]],"date-time":"2017-07-01T00:00:00Z","timestamp":1498867200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/tcsi.2017.2680433","type":"journal-article","created":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T04:49:35Z","timestamp":1490244575000},"page":"1803-1814","source":"Crossref","is-referenced-by-count":9,"title":["Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches"],"prefix":"10.1109","volume":"64","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4673-1891","authenticated-orcid":false,"given":"Wael M.","family":"Elsharkasy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amin","family":"Khajeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1849-083X","authenticated-orcid":false,"given":"Ahmed M.","family":"Eltawil","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fadi J.","family":"Kurdahi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2041377"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2010.5682949"},{"journal-title":"Variation-Aware Design of Custom Integrated Circuits A Hands-on Field Guide","year":"2012","author":"mcconaghy","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803943"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630154"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413168"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-17752-1_18"},{"key":"ref17","first-page":"1","article-title":"A 0.42 V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SoC","author":"dhong","year":"2014","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2366811"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2366813"},{"key":"ref28","first-page":"284","article-title":"32\/28 nm educational design kit: Capabilities, deployment and future","author":"goldman","year":"2013","journal-title":"Proc IEEE Asia Pacific Conf Postgraduate Res Microelectron Electron (PrimeAsia)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784500"},{"journal-title":"Synopsys 32\/28 nm iPDKs","year":"2017","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.24"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2284647"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346504"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2276100"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.962279"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2007.4430305"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105397"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2041376"},{"journal-title":"Closing the Gap Between ASIC & Custom Tools and Techniques for High-Performance ASIC Design","year":"2002","author":"chinnery","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0433"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-6196-4"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852164"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654219"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090685"},{"key":"ref26","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-319-01997-0","author":"alioto","year":"2015","journal-title":"Flip-Flop Design in Nanometer CMOS From High Speed to Low Energy"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-68953-1"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/7956380\/07885016.pdf?arnumber=7885016","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,22]],"date-time":"2023-08-22T19:39:33Z","timestamp":1692733173000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7885016\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":29,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2017.2680433","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2017,7]]}}}