{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:23:15Z","timestamp":1772119395287,"version":"3.50.1"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2017,8,1]],"date-time":"2017-08-01T00:00:00Z","timestamp":1501545600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2017,8]]},"DOI":"10.1109\/tcsi.2017.2685634","type":"journal-article","created":{"date-parts":[[2017,3,30]],"date-time":"2017-03-30T19:20:22Z","timestamp":1490901622000},"page":"2063-2072","source":"Crossref","is-referenced-by-count":8,"title":["SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis"],"prefix":"10.1109","volume":"64","author":[{"given":"Tae Hoon","family":"Choi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hanwool","family":"Jeong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Younghwi","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juhyun","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0757-2581","authenticated-orcid":false,"given":"Seong-Ook","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032698"},{"key":"ref12","first-page":"87","article-title":"Modeling FET variation within a chip as a function of circuit design and layout choices","author":"watts","year":"2005","journal-title":"Proc NSTI Nanotech Workshop Compact Modeling"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2423634"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2267745"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/43.273749"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-71752-4_3"},{"key":"ref18","first-page":"3.7.1","article-title":"A 14nm logic technology featuring \n$2^{nd}$\n  -generation FinFET, air-gapped interconnects, self-aligned double patterning and a \n$0.0588~\\mu$\nm2 SRAM cell size","author":"natarajan","year":"2014","journal-title":"Proc IEEE Int Electron Devices Meeting"},{"key":"ref19","first-page":"150t","article-title":"High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology","author":"giles","year":"2015","journal-title":"Proc Symp VLSI Technol (VLSI-Technol )"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146930"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883344"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2010.5450410"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681593"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2404895"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187551"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2011845"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146928"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560101"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2005.1497065"},{"key":"ref22","author":"weste","year":"2011","journal-title":"Integrated Circuit Design"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2362842"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2010.04.010"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2008.4588544"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/7992992\/07890466.pdf?arnumber=7890466","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:39:36Z","timestamp":1641987576000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7890466\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,8]]},"references-count":24,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2017.2685634","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,8]]}}}