{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,30]],"date-time":"2025-04-30T04:48:48Z","timestamp":1745988528632,"version":"3.37.3"},"reference-count":51,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/tcsi.2017.2712363","type":"journal-article","created":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T21:23:27Z","timestamp":1497561807000},"page":"163-174","source":"Crossref","is-referenced-by-count":16,"title":["Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM"],"prefix":"10.1109","volume":"65","author":[{"given":"Taehui","family":"Na","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Byungkyu","family":"Song","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jung Pill","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seung H.","family":"Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0757-2581","authenticated-orcid":false,"given":"Seong-Ook","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2010.2075920"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2536639"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2170778"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234301"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2606438"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2582203"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2260365"},{"key":"ref36","first-page":"296","article-title":"A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance","author":"kim","year":"2011","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2015.7273482"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2166282"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2468993"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2357054"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2453192"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.actamat.2012.10.036"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424368"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523238"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062962"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2235013"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2612235"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2427931"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2294095"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487706"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1049\/el.2013.2319"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527473"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1080\/09506608.2016.1204097"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2296136"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2013.2243133"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2327337"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2326797"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898058"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.909751"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424382"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2220458"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2530883"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref4","first-page":"258","article-title":"A 64Mb MRAM with clamped-reference and adequate-reference schemes","author":"tsuchida","year":"2010","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2224256"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2804"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724549"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2182053"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2020721"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409770"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187506"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2088143"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006428"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2239320"},{"key":"ref42","first-page":"450","article-title":"A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture","author":"tsuji","year":"2004","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.825251"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2230515"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810048"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8248584\/07949043.pdf?arnumber=7949043","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:28:01Z","timestamp":1642004881000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7949043\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":51,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2017.2712363","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2018,1]]}}}