{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T00:28:18Z","timestamp":1787012898315,"version":"build-2736575974"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003621","name":"National Research Foundation of Korea through the Korean Government within the Ministry of Science, ICT and Future Planning","doi-asserted-by":"publisher","award":["2016R1E1A1A02922127"],"award-info":[{"award-number":["2016R1E1A1A02922127"]}],"id":[{"id":"10.13039\/501100003621","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/tcsi.2017.2717900","type":"journal-article","created":{"date-parts":[[2017,7,27]],"date-time":"2017-07-27T14:08:27Z","timestamp":1501164507000},"page":"331-342","source":"Crossref","is-referenced-by-count":26,"title":["A 1-V 10-Gb\/s\/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces"],"prefix":"10.1109","volume":"65","author":[{"given":"Junyoung","family":"Song","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sewook","family":"Hwang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hyun-Woo","family":"Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4379-7905","authenticated-orcid":false,"given":"Chulwoo","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062921"},{"key":"ref11","first-page":"320","article-title":"1V 10Gb\/s\/pin single-ended transceiver with controllable activeinductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces","author":"song","year":"2015","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","first-page":"272c","article-title":"A 10 Gb\/s 2-IIR-tap DFE receiver with 35 dB loss compensation in 65-nm CMOS","author":"elhadidy","year":"2013","journal-title":"Proc IEEE Symp VLSI Circuits (VLSIC)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2402218"},{"key":"ref14","first-page":"312","article-title":"An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb\/s\/pin graphics DRAM interface","author":"song","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031015"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845563"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2280308"},{"key":"ref18","first-page":"132","article-title":"A 0.4 mW\/Gb\/s 16 Gb\/s near-ground receiver front-end with replica transconductance termination calibration","author":"kaviani","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref19","first-page":"240","article-title":"A sub-1.0V 20nm 5Gb\/s\/pin post-LPDDR3 I\/O interface with low voltage-swing terminated logic and adaptive calibration scheme for mobile application","author":"cho","year":"2013","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref4","year":"2012"},{"key":"ref3","year":"2011"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2411791"},{"key":"ref5","year":"2014"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884342"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487627"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-02381-6"},{"key":"ref1","first-page":"1","article-title":"High-bandwidth memory interface design","author":"kim","year":"2013","journal-title":"ISSCC Tutorial"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2412688"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2359665"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185184"},{"key":"ref21","author":"tsividis","year":"1987","journal-title":"Operation and Modeling of the MOS Transistor"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596773"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279053"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8248584\/07994688.pdf?arnumber=7994688","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:28:01Z","timestamp":1641986881000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7994688\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":24,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2017.2717900","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,1]]}}}