{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T12:04:58Z","timestamp":1740139498569,"version":"3.37.3"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council, Taiwan","doi-asserted-by":"publisher","award":["MOST105-2218-E-002-024","MOST104-2220-E-002-003","MOST104-2220-E-182-001"],"award-info":[{"award-number":["MOST105-2218-E-002-024","MOST104-2220-E-002-003","MOST104-2220-E-182-001"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100005795","name":"Chang Gung Medical Research Program","doi-asserted-by":"publisher","award":["BMRPA77"],"award-info":[{"award-number":["BMRPA77"]}],"id":[{"id":"10.13039\/501100005795","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/tcsi.2017.2719283","type":"journal-article","created":{"date-parts":[[2017,7,14]],"date-time":"2017-07-14T18:31:16Z","timestamp":1500057076000},"page":"141-153","source":"Crossref","is-referenced-by-count":2,"title":["Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement"],"prefix":"10.1109","volume":"65","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7451-4261","authenticated-orcid":false,"given":"Bing-Chen","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3412-6958","authenticated-orcid":false,"given":"I-Chyn","family":"Wey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195479"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2426113"},{"journal-title":"VLSI Digital Signal Processing Systems Design and Implementation","year":"2007","author":"parhi","key":"ref37"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870450"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2160753"},{"key":"ref34","first-page":"1","article-title":"An 80 nW retention 11.7 pJ\/cycle active subthreshold ARM Cortex-M0+ subsystem in 65 nm CMOS for WSN applications","author":"myers","year":"2015","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.122"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2010767"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2036764"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239096"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"883","DOI":"10.1109\/TVLSI.2008.2012054","article-title":"Asynchronous computing in sense amplifier-based pass transistor logic","volume":"17","author":"liu","year":"2009","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2039684"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2342932"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165578"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2222811"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-16136-5"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref27","first-page":"188","article-title":"The phoenix processor: A 30 pW platform for sensor applications","author":"seok","year":"2008","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref3","first-page":"260","article-title":"A 21.5 M-query-vectors\/s 3.37 nJ\/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14 nm tri-gate CMOS","author":"kaul","year":"2016","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref6","first-page":"868","article-title":"Theoretical and practical limits of dynamic voltage scaling","author":"bo zhai","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"journal-title":"CMOS VLSI Design A Circuits and Systems Perspective","year":"2011","author":"weste","key":"ref29"},{"key":"ref5","first-page":"264","article-title":"A 1.42 TOPS\/W deep convolutional neural network recognition processor for intelligent IoE systems","author":"sim","year":"2016","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852162"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.837945"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418005"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2177004"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418003"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917505"},{"journal-title":"Skew-Tolerant Circuit Design","year":"2001","author":"harris","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2169311"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2332134"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.876378"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031813"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2159528"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8248584\/07981366.pdf?arnumber=7981366","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:28:00Z","timestamp":1642004880000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7981366\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":37,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2017.2719283","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2018,1]]}}}