{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T04:58:06Z","timestamp":1782968286916,"version":"3.54.5"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Ministry of Science and Technology, R.O.C.","award":["MOST 104-2218-E-110-010-MY2"],"award-info":[{"award-number":["MOST 104-2218-E-110-010-MY2"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/tcsi.2017.2725338","type":"journal-article","created":{"date-parts":[[2017,7,20]],"date-time":"2017-07-20T18:10:52Z","timestamp":1500574252000},"page":"118-129","source":"Crossref","is-referenced-by-count":50,"title":["VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications"],"prefix":"10.1109","volume":"65","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9045-5847","authenticated-orcid":false,"given":"Xin-Yu","family":"Shih","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hong-Ru","family":"Chou","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yue-Qu","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2194315"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7539000"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2350017"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2178275"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/PRIMEASIA.2010.5604921"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2542583"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7539011"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2264695"},{"key":"ref35","first-page":"57","article-title":"A mixed-radix pipeline FFT processor with trivial multiplications for LTE uplink","author":"kim","year":"2016","journal-title":"proc IEEE int symp on consumer Electronics (ISCE)"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6854339"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052211"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2176163"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2003.1205465"},{"key":"ref12","first-page":"342","article-title":"A 0.27 V 30 MHz 17.7 nJ\/transform 1024-pt complex FFT core with super-pipelining","author":"seok","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2016.7451037"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2567784"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2011.6126703"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICDSP.2015.7251982"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2016.43"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1049\/el.2012.0577"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1981.1163631"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e91-a.4.1206"},{"key":"ref4","first-page":"1","article-title":"Twiddle factor transformation for pipelined FFT processing","author":"park","year":"2007","journal-title":"Proc 25th Int Conf Comput Design"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852007"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TENCON.2016.7848299"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2544838"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2365586"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICSESS.2014.6933587"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1978.1163084"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2012.6180313"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IMTC.2007.379470"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICIEV.2013.6572680"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TIECI.1978.351511"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1986.1164826"},{"key":"ref22","first-page":"257","article-title":"Designing pipeline FFT processor for OFDM (de)modulation","author":"he","year":"1998","journal-title":"Proc URSI Int Symp Signals Systems Electronics (ISSSE)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.835815"},{"key":"ref42","doi-asserted-by":"crossref","first-page":"305","DOI":"10.1109\/TVLSI.2009.2032553","article-title":"Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding","volume":"19","author":"lin","year":"2011","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref24","first-page":"489","article-title":"Multiplier-less based architecture for variable-length FFT hardware implementation","author":"cuong","year":"2012","journal-title":"Proc Intl Conf Communications and Electronics (ICCE)"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2304834"},{"key":"ref23","first-page":"2530","article-title":"Pipelined structure based on radix-22 FFT algorithm","author":"bi","year":"2011","journal-title":"Proc IEEE Ind Electron Appl Conf"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2009.5373805"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.910771"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8248584\/07987022.pdf?arnumber=7987022","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:27:59Z","timestamp":1642004879000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7987022\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":42,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2017.2725338","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,1]]}}}