{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,26]],"date-time":"2025-12-26T07:15:06Z","timestamp":1766733306237,"version":"3.37.3"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"NSF CAREER","award":["1149464"],"award-info":[{"award-number":["1149464"]}]},{"name":"Spork Fellowship"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/tcsi.2017.2767585","type":"journal-article","created":{"date-parts":[[2017,11,27]],"date-time":"2017-11-27T19:06:36Z","timestamp":1511809596000},"page":"2035-2047","source":"Crossref","is-referenced-by-count":10,"title":["Four Monolithically Integrated Switched-Capacitor DC\u2013DC Converters With Dynamic Capacitance Sharing in 65-nm CMOS"],"prefix":"10.1109","volume":"65","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3675-6486","authenticated-orcid":false,"given":"Ivan","family":"Bukreyev","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2385-619X","authenticated-orcid":false,"given":"Christopher","family":"Torng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Waclaw","family":"Godycki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2835-667X","authenticated-orcid":false,"given":"Christopher","family":"Batten","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alyssa","family":"Apsel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2316919"},{"key":"ref11","first-page":"344","article-title":"A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28 nm CMOS","author":"jiang","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"Proc Int Symp High-Perform Comput Archit"},{"key":"ref13","first-page":"372","article-title":"A sub-ns response fully integrated battery-connected switched-capacitor voltage regulator delivering 0.19 W\/mm2 at 73% efficiency","author":"le","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2159054"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168942"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488949"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2076550"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.12"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2605662"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417986"},{"key":"ref27","first-page":"316c","article-title":"A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28 nm FDSOI","author":"zimmer","year":"2015","journal-title":"Proc VLSIC"},{"key":"ref3","first-page":"1","article-title":"A fully integrated gearbox capacitive DC\/DC-converter in 90 nm CMOS: Optimization, control and measurements","author":"van breussegem","year":"2010","journal-title":"Proc COMPEL"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2747931"},{"key":"ref5","first-page":"55","article-title":"A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3 A\/mm2","author":"chang","year":"2010","journal-title":"Proc Symp Very Large Scale Integr Circuits"},{"journal-title":"Intel Turbo Boost Technology in Intel Core Microarchitecture (Nehalem) Based Processors","year":"2008","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.52"},{"key":"ref2","first-page":"336c","article-title":"A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6 mV output ripple","author":"bang","year":"2015","journal-title":"Proc VLSIC"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2297402"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037717"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.21236\/ADA538398"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2399025"},{"key":"ref21","first-page":"210","article-title":"A 32 nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55 W\/mm2 at 81% efficiency","author":"le","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"journal-title":"DCDC Performance Survey","year":"2017","author":"steyaert","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2015.2478850"},{"journal-title":"Intelligent power allocation","year":"2017","author":"wang","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2013.2242094"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/8919\/8355985\/8120204-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8355985\/08120204.pdf?arnumber=8120204","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:51:35Z","timestamp":1649443895000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8120204\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":27,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2017.2767585","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2018,6]]}}}