{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T12:05:21Z","timestamp":1740139521002,"version":"3.37.3"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/tcsi.2018.2825362","type":"journal-article","created":{"date-parts":[[2018,4,24]],"date-time":"2018-04-24T18:54:33Z","timestamp":1524596073000},"page":"3543-3554","source":"Crossref","is-referenced-by-count":6,"title":["An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture"],"prefix":"10.1109","volume":"65","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4418-2200","authenticated-orcid":false,"given":"N.","family":"Prasad","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Indrajit","family":"Chakrabarti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Santanu","family":"Chattopadhyay","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.857181"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.13.0113.0032"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.3093"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2091686"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2012.10.004"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2240708"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2653838"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/26.871381"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.822396"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.853892"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.903957"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.1993.397441"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.918148"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1967.1054010"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/78.236512"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.890617"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2017.10.011"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2008.4580153"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378711"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAMOS.2009.5289227"},{"article-title":"Cognitive radio—An integrated agent architecture for software defined radio","year":"2000","author":"mitola","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1080\/21681724.2015.1028472"},{"journal-title":"Design Compiler","year":"2017","key":"ref22"},{"journal-title":"ModelSim","year":"2017","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2012.6414981"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2382108"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"1358","DOI":"10.1109\/TVLSI.2008.2000514","article-title":"Unified convolutional\/turbo decoder design using tile-based timing analysis of VA\/MAP kernel","volume":"16","author":"li","year":"2008","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002428"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8453271\/08345766.pdf?arnumber=8345766","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:09:39Z","timestamp":1642003779000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8345766\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":30,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2018.2825362","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2018,10]]}}}