{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:13:00Z","timestamp":1781885580418,"version":"3.54.5"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001459","name":"Singaporean Ministry of Education","doi-asserted-by":"crossref","award":["MOE2014-T2-2-129"],"award-info":[{"award-number":["MOE2014-T2-2-129"]}],"id":[{"id":"10.13039\/501100001459","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/tcsi.2018.2828611","type":"journal-article","created":{"date-parts":[[2018,5,21]],"date-time":"2018-05-21T23:25:38Z","timestamp":1526945138000},"page":"3338-3348","source":"Crossref","is-referenced-by-count":37,"title":["Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories"],"prefix":"10.1109","volume":"65","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0499-2938","authenticated-orcid":false,"given":"Quang-Kien","family":"Trinh","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sergio","family":"Ruocco","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4127-8258","authenticated-orcid":false,"given":"Massimo","family":"Alioto","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"296","article-title":"A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance","author":"kim","year":"2011","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2015.7150282"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2453192"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2749522"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2239671"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2011.6035047"},{"key":"ref16","author":"fong","year":"2013","journal-title":"SPICE Models for Magnetic Tunnel Junctions Based on Monodomain Approximation"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1038\/nmat1257"},{"key":"ref18","first-page":"1","article-title":"45nm low power CMOS logic compatible embedded STT-MRAM utilizing a reverse-connection 1T\/1MTJ cell","author":"lin","year":"2009","journal-title":"IEDM Tech Dig"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2010.2042041"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818145"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2015455"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547702"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2582203"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2170778"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2088143"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.825251"},{"key":"ref2","year":"2013","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2272587"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2463585.2463589"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/INTMAG.2015.7156502"},{"key":"ref22","first-page":"13","article-title":"Delay-locked loops&#x2014;An overview","author":"yang","year":"2003","journal-title":"Phase-Locking in High Performance Systems"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055315"},{"key":"ref24","author":"walpole","year":"2006","journal-title":"Probability & Statistics for Engineers & Scientists"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857370"},{"key":"ref26","author":"weste","year":"2010","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8453271\/08361484.pdf?arnumber=8361484","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:09:39Z","timestamp":1642003779000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8361484\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":27,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2018.2828611","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,10]]}}}