{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,26]],"date-time":"2026-06-26T14:03:24Z","timestamp":1782482604286,"version":"3.54.5"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"National Science and Technology Major Project","award":["2017ZX01030101"],"award-info":[{"award-number":["2017ZX01030101"]}]},{"DOI":"10.13039\/501100008081","name":"Southeast University","doi-asserted-by":"publisher","award":["2242018K40100"],"award-info":[{"award-number":["2242018K40100"]}],"id":[{"id":"10.13039\/501100008081","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Beijing Municipal of Science and Technology","award":["Z161100000216149"],"award-info":[{"award-number":["Z161100000216149"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2019,1]]},"DOI":"10.1109\/tcsi.2018.2854277","type":"journal-article","created":{"date-parts":[[2018,8,17]],"date-time":"2018-08-17T18:43:44Z","timestamp":1534531424000},"page":"239-250","source":"Crossref","is-referenced-by-count":10,"title":["Addressing Failure and Aging Degradation in MRAM\/MeRAM-on-FDSOI Integration"],"prefix":"10.1109","volume":"66","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9794-8049","authenticated-orcid":false,"given":"Hao","family":"Cai","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6917-2199","authenticated-orcid":false,"given":"You","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lirida Alves","family":"de Barros Naviner","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xinning","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5520-1326","authenticated-orcid":false,"given":"Weiwei","family":"Shan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8379-0321","authenticated-orcid":false,"given":"Jun","family":"Yang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3169-6034","authenticated-orcid":false,"given":"Weisheng","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357123"},{"key":"ref38","first-page":"1","article-title":"45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T\/1MTJ cell","author":"lin","year":"2009","journal-title":"IEDM Tech Dig"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2017.2660530"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2533438"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2015.2438017"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2295026"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2155658"},{"key":"ref36","first-page":"424","article-title":"Ultra-wide body-bias range LDPC decoder in 28 nm UTBB FDSOI technology","author":"flatresse","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref35","first-page":"3b.1.1","article-title":"28 nm node bulk vs FDSOI reliability comparison","author":"federspiel","year":"2012","journal-title":"Proc IEEE Int Rel Phys Symp (IRPS)"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6860597"},{"key":"ref28","first-page":"123","article-title":"A novel circuit design of true random number generator using magnetic tunnel junction","author":"wang","year":"2016","journal-title":"IEEE\/ACM Int Symp on Nanoscale Arch (NANOARCH)"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2015.2416689"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2172644"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250885"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2016.2608910"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2670502"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2764520"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2231015"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2628772"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1038\/srep04105"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1063\/1.3443658"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2621344"},{"key":"ref11","first-page":"1146","article-title":"Design considerations for reliable OxRAM-based non-volatile flip-flops in 28 nm FD-SOI technology","author":"jovanovic","year":"2016","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2412960"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2017.2703985"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2015.27"},{"key":"ref14","first-page":"1","article-title":"A 3.3 ns-access-time \n$71.2~\\mu \\text{W}$\n\/MHz 1 Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture","author":"noguchi","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870428"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1063\/1.4867129"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2239671"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2362853"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2023192"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2224256"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2024"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547704"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2008.406"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1038\/nmat3171"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/MCE.2017.2755218"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2633004"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2016.2584140"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/IPFA.2008.4588195"},{"key":"ref48","first-page":"1","article-title":"A fast, flexible, positive and negative adaptive body-bias generator in 28 nm FDSOI","author":"blagojevi?","year":"2016","journal-title":"Proc IEEE Symp VLSI Circuits (VLSI)"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.53"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2135470"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.10.002"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474366"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2012.2224375"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8566198\/08439066.pdf?arnumber=8439066","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:12:55Z","timestamp":1657746775000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8439066\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1]]},"references-count":49,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2018.2854277","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,1]]}}}