{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T18:25:26Z","timestamp":1772907926897,"version":"3.50.1"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Grants-in-Aid for Scientific Research from JSPS and a research fund from NEC"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/tcsi.2018.2882474","type":"journal-article","created":{"date-parts":[[2018,12,4]],"date-time":"2018-12-04T19:54:35Z","timestamp":1543953275000},"page":"1517-1530","source":"Crossref","is-referenced-by-count":32,"title":["Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme"],"prefix":"10.1109","volume":"66","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5583-4895","authenticated-orcid":false,"given":"Heming","family":"Sun","sequence":"first","affiliation":[]},{"given":"Zhengxue","family":"Cheng","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0451-221X","authenticated-orcid":false,"given":"Amir Masoud","family":"Gharehbaghi","sequence":"additional","affiliation":[]},{"given":"Shinji","family":"Kimura","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Fujita","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","first-page":"188c","article-title":"A 1062Mpixels\/s 8192×4320p high efficiency video coding (H.265) encoder chip","author":"tsai","year":"2013","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref32","year":"2018","journal-title":"Joint Exploration Model (JEM-7 0)"},{"key":"ref31","author":"bjontegaard","year":"2001","journal-title":"Calculation of Average PSNR Differences Between RD-Curves"},{"key":"ref30","year":"2018","journal-title":"HEVC Test Model(HM-16 0)"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050263"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742917"},{"key":"ref10","first-page":"950","article-title":"A new high throughput VLSI architecture for H.264 transform and quantization","author":"peng","year":"2007","journal-title":"Proc Int Conf ASIC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VCIP.2014.7051538"},{"key":"ref12","first-page":"677","article-title":"Fully pipelined DCT\/IDCT\/Hadamard unified transform architecture for HEVC Codec","author":"zhu","year":"2013","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICME.2012.7"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2012.6466832"},{"key":"ref15","first-page":"1668","article-title":"High-performance multiplierless transform architecture for HEVC","author":"zhao","year":"2013","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref16","first-page":"1376","article-title":"Flexible integer DCT architectures for HEVC","author":"park","year":"2013","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1977.1093941"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2013.2276862"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2295022"},{"key":"ref28","author":"bross","year":"2018","journal-title":"Versatile Video Coding (Draft 2)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2015.2428571"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/83.869177"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221191"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.2008058"},{"key":"ref29","author":"bossen","year":"2013","journal-title":"Common HM Test Conditions and Software Reference Configurations"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"551","DOI":"10.1109\/TCSII.2010.2048477","article-title":"A low-cost very large scale integration architecture for multistandard inverse transform","volume":"57","author":"qi","year":"2010","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2158265"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.2008058"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2014.7025421"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2010.5775075"},{"key":"ref1","year":"2013","journal-title":"High Efficiency Video Coding"},{"key":"ref20","first-page":"2714","article-title":"Adaptive approximated DCT architectures for HEVC","volume":"27","author":"masera","year":"2017","journal-title":"IEEE Trans Circuits Syst Video Technol"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2016.2556578"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2360763"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E99.A.2375"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2224751"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2014.6868629"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/JSSC.2015.2465857","article-title":"A 0.5 nJ\/pixel 4 K H.265\/HEVC codec LSI for multi-format smartphone applications","volume":"51","author":"ju","year":"2016","journal-title":"IEEE J Solid-State Circuits"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8667917\/08558684.pdf?arnumber=8558684","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:55:55Z","timestamp":1657745755000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8558684\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":35,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2018.2882474","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,4]]}}}