{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,12]],"date-time":"2026-05-12T16:55:40Z","timestamp":1778604940540,"version":"3.51.4"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["MOST 107-2221-E-009-048"],"award-info":[{"award-number":["MOST 107-2221-E-009-048"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/tcsi.2019.2892065","type":"journal-article","created":{"date-parts":[[2019,1,31]],"date-time":"2019-01-31T20:34:40Z","timestamp":1548966880000},"page":"2454-2467","source":"Crossref","is-referenced-by-count":14,"title":["Analytical Noise Optimization of Single-\/Dual-Band MOS LNAs With Substrate and Metal Loss Effects of Inductors"],"prefix":"10.1109","volume":"66","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5151-910X","authenticated-orcid":false,"given":"Wei Ling","family":"Chang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7701-0202","authenticated-orcid":false,"given":"Chinchun","family":"Meng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jung-Hung","family":"Ni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kai-Chun","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chih-Kai","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Po-Yi","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yen-Lin","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/APMC.2017.8251508"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2180436"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2012.2237037"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2004.842510"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2015.7387494"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479039"},{"key":"ref13","first-page":"ts6.3.1","article-title":"Power saving and noise reduction of 28 nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology","author":"wang","year":"2015","journal-title":"Proc IEEE Int'l 3D Systems Integration Conf (3DIC)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2004.827014"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/82.964996"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/S0065-2539(08)61205-6"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2073890"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.875188"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/4.668989"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2771940"},{"key":"ref4","first-page":"519","article-title":"Design optimization of single-\/dual-band FET LNAs using noise transformation matrix","volume":"64","author":"hsiao","year":"2016","journal-title":"IEEE Trans Microw Theory Techn"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2013.2280116"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2012.2187882"},{"key":"ref6","first-page":"1","article-title":"Analog\/RF wonderland: Circuit and technology co-optimization in advanced FinFET technology","author":"hsueh","year":"2016","journal-title":"Proc IEEE Symp VLSI Technol"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2710057"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2548259"},{"key":"ref8","first-page":"350","article-title":"A 40 nm dual-band 3-stream 802.11a\/b\/g\/n\/ac MIMO WLAN SoC with 1.1 Gb\/s over-the-air throughput","author":"he","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.847490"},{"key":"ref2","first-page":"1","article-title":"A 12.7 dBm IIP3, 1.34 dB NF, 4.9 GHz–5.9 GHz 802.11a\/n LNA in 0.13 \n$\\mu\\text{m}$\n PD-SOI CMOS with body-contacted transistor","author":"paulin","year":"2016","journal-title":"IEEE MTT-S Int Microw Symp Dig"},{"key":"ref9","first-page":"1","article-title":"100-mV 44-\n$\\mu\\text{W}$\n 2.4-GHz LNA in 16 nm FinFET technology","author":"lu","year":"2016","journal-title":"IEEE MTT-S Int Microw Symp Dig"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.1999.805227"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2017.2760834"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2006208"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"874","DOI":"10.1109\/T-ED.1973.17761","article-title":"changes of the four noise parameters due to general changes of linear two-port circuits","volume":"20","author":"hartmann","year":"1973","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2781369"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2649844"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/22.808983"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2007.903836"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8741038\/08630666.pdf?arnumber=8630666","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:43:21Z","timestamp":1657745001000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8630666\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":32,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2019.2892065","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,7]]}}}