{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T16:02:58Z","timestamp":1777651378443,"version":"3.51.4"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006602","name":"Air Force Research Laboratory","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006602","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2019,6]]},"DOI":"10.1109\/tcsi.2019.2902102","type":"journal-article","created":{"date-parts":[[2019,4,25]],"date-time":"2019-04-25T21:45:54Z","timestamp":1556228754000},"page":"2037-2050","source":"Crossref","is-referenced-by-count":22,"title":["Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing"],"prefix":"10.1109","volume":"66","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1025-8198","authenticated-orcid":false,"given":"Roman","family":"Fragasse","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4476-0442","authenticated-orcid":false,"given":"Ramy","family":"Tantawy","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4423-5675","authenticated-orcid":false,"given":"Brian","family":"Dupaix","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6617-5039","authenticated-orcid":false,"given":"Trevor","family":"Dean","sequence":"additional","affiliation":[]},{"given":"Daron","family":"Disabato","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5817-8539","authenticated-orcid":false,"given":"Matthew R.","family":"Belz","sequence":"additional","affiliation":[]},{"given":"Dale","family":"Smith","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2896-3429","authenticated-orcid":false,"given":"Jamin","family":"Mccue","sequence":"additional","affiliation":[]},{"given":"Waleed","family":"Khalil","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672108"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.953479"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280731"},{"key":"ref13","first-page":"57","article-title":"Improving the speed and power of compilable SRAM using dual-mode self-timed technique","author":"chang","year":"2007","journal-title":"Proc IEEE Int Workshop Memory Technol Design Test"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914328"},{"key":"ref15","first-page":"242","article-title":"13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28 nm CMOS","author":"giridhar","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2347707"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2085970"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2018.8399941"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2024663"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1002\/9780470891179"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.883204"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2014.6946003"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.881204"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1328161"},{"key":"ref2","author":"harris","year":"1994","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2223036"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164294"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.917991"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032698"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/4.173122"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8715688\/08698826.pdf?arnumber=8698826","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:13:39Z","timestamp":1657746819000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8698826\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6]]},"references-count":22,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2019.2902102","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,6]]}}}