{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,23]],"date-time":"2026-10-23T20:19:25Z","timestamp":1792786765696,"version":"4.5.0"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"CNPq, CAPES, and FAPERGS"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2019,6]]},"DOI":"10.1109\/tcsi.2019.2907722","type":"journal-article","created":{"date-parts":[[2019,4,25]],"date-time":"2019-04-25T17:45:54Z","timestamp":1556214354000},"page":"2175-2187","source":"Crossref","is-referenced-by-count":18,"title":["Transistor Count Reduction by Gate Merging"],"prefix":"10.1109","volume":"66","author":[{"given":"Calebe Micael de Oliveira","family":"Conceicao","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5781-5858","authenticated-orcid":false,"given":"Ricardo Augusto da Luz","family":"Reis","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2448675"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2410764"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647772"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228857"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2016.90"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168916"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2017.8292073"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724596"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.79"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2015.09.001"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2305847"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2012.6328962"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2011.6122380"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2016.7833673"},{"key":"ref17","first-page":"163","article-title":"Reducing the number of transistors with gate clustering","author":"concei\u00e7\u00e3o","year":"2016","journal-title":"Proc IEEE Lat Amer Symp Circuits Syst (LASCAS)"},{"key":"ref18","first-page":"186","article-title":"A cell clustering technique to reduce transistor count","author":"concei\u00e7\u00e3o","year":"2017","journal-title":"Proc IEEE Int Conf Electronics Circuits Syst (ICECS)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.74"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2001.934194"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2011.6144656"},{"key":"ref27","first-page":"102","article-title":"An integrated algorithm for combined placement and libraryless technology mapping","author":"jiang","year":"1999","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref3","first-page":"116","article-title":"Technology mapping in MIS","author":"detjens","year":"1987","journal-title":"Proc Int Conf Comput Aided Design"},{"key":"ref6","first-page":"21","article-title":"Challenges and emerging technologies for system integration beyond the end of the roadmap of nano-CMOS","author":"bampi","year":"2009","journal-title":"VLSI-SoC Technologies for Systems Integration"},{"key":"ref29","first-page":"5","article-title":"Tree-based transistor topology extraction algorithm for library-free logic synthesis","author":"xue","year":"2004","journal-title":"Proc IEEE Int Conf Semiconductor Electronics"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2017.7993513"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1988.122551"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-35311-1_25"},{"key":"ref2","author":"micheli","year":"1994","journal-title":"Synthesis and Optimization of Digital Circuits"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.1999.803115"},{"key":"ref1","author":"rabaey","year":"2002","journal-title":"Digital Integrated Circuits"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938108"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2015.10.018"},{"key":"ref21","article-title":"Building transistor-level networks following the lower bound on the number of stacked switches","author":"schneider","year":"2007"},{"key":"ref24","first-page":"1","article-title":"Reducing the amount of transistors by gate merging","author":"da silva","year":"2018","journal-title":"Proc IEEE Lat Amer Symp Circuits Syst (LASCAS)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2014.6820314"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643608"},{"key":"ref25","first-page":"740","article-title":"A physical synthesis design flow based on virtual components","author":"moraes","year":"2000","journal-title":"Proc 15th Des Circuits Integr Syst Conf"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8715688\/08698854.pdf?arnumber=8698854","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T17:13:39Z","timestamp":1657732419000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8698854\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6]]},"references-count":36,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2019.2907722","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,6]]}}}