{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,26]],"date-time":"2025-04-26T05:05:56Z","timestamp":1745643956420,"version":"3.37.3"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002347","name":"Bundesministerium f\u00fcr Bildung und Forschung","doi-asserted-by":"publisher","award":["16ES0303"],"award-info":[{"award-number":["16ES0303"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2020,2]]},"DOI":"10.1109\/tcsi.2019.2926149","type":"journal-article","created":{"date-parts":[[2019,7,22]],"date-time":"2019-07-22T23:21:36Z","timestamp":1563837696000},"page":"401-414","source":"Crossref","is-referenced-by-count":1,"title":["Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4303-031X","authenticated-orcid":false,"given":"Jahnavi","family":"Kasturi Rangan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nasim","family":"Pour Aryan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5974-4790","authenticated-orcid":false,"given":"Jens","family":"Bargfrede","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lantao","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Funke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7626-1958","authenticated-orcid":false,"given":"Helmut","family":"Graeb","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"111","article-title":"IC performance prediction for test cost reduction","author":"lee","year":"1999","journal-title":"Proc IEEE Int Symp Semicond Manuf Conf"},{"journal-title":"ILP Package","year":"2017","key":"ref11"},{"journal-title":"IBM ILOG CPLEX Optimizer","year":"2010","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2018.8617873"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-2269-3"},{"key":"ref15","first-page":"1","article-title":"Timing variability analysis of digital CMOS circuits","author":"rangan","year":"2017","journal-title":"Proc ITG\/GMM\/GI-Symp"},{"journal-title":"Static Timing Analysis for Nanometer Designs A Practical Approach","year":"2009","author":"bhasker","key":"ref16"},{"journal-title":"Multilevel Optimization in VLSICAD","year":"2003","author":"du","key":"ref17"},{"key":"ref18","first-page":"1027","article-title":"K-means++: The advantages of careful seeding","author":"arthur","year":"2007","journal-title":"Proc Annu ACM-SIAM Symp Discrete Algorithm"},{"journal-title":"Cluster Analysis","year":"1974","author":"everitt","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2005.863244"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/NATW.2014.21"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2013.6569366"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090692"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref7","first-page":"1","article-title":"Characterization and compensation of performance variability using on-chip monitors","author":"islam","year":"2014","journal-title":"Proc IEEE Int Sym VLSI Tech Syst and Appl (VLSI-TSA)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2478921"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187559"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.29"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8972641\/08768360.pdf?arnumber=8768360","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T16:50:25Z","timestamp":1651078225000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8768360\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2]]},"references-count":19,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2019.2926149","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2020,2]]}}}