{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T15:13:47Z","timestamp":1781622827091,"version":"3.54.5"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["NSF-CCF-1903951"],"award-info":[{"award-number":["NSF-CCF-1903951"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["NSF-CCF-1740225"],"award-info":[{"award-number":["NSF-CCF-1740225"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2018-NC-2762"],"award-info":[{"award-number":["2018-NC-2762"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100004358","name":"Samsung","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/tcsi.2019.2958568","type":"journal-article","created":{"date-parts":[[2019,12,25]],"date-time":"2019-12-25T20:54:00Z","timestamp":1577307240000},"page":"1333-1343","source":"Crossref","is-referenced-by-count":87,"title":["Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6148-7711","authenticated-orcid":false,"given":"Xiaochen","family":"Peng","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rui","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0068-3652","authenticated-orcid":false,"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref30","first-page":"1","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2015","journal-title":"Proc of the Int Conf on Learning Representations (ICLR)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7539046"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2789723"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702715"},{"key":"ref13","first-page":"1","article-title":"Training and inference with integers in deep neural networks","author":"wu","year":"2018","journal-title":"Proc of the Int Conf on Learning Representations (ICLR)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-015-0816-y"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"ref19","first-page":"1","article-title":"Binarized neural networks","author":"hubara","year":"2016","journal-title":"Proc 30th Conf Neural Inf Process Syst (NIPS)"},{"key":"ref28","first-page":"1423","article-title":"XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks","author":"sun","year":"2018","journal-title":"Proc Des Autom Test Eur (DATE) Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref27","first-page":"854","article-title":"Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip","author":"chen","year":"2015","journal-title":"Proc Des Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870350"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2015.2481819"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662392"},{"key":"ref8","first-page":"212","article-title":"A 3.6 Mb 10.1 Mb\/mm2 embedded non-volatile ReRAM macro in 22 nm FinFET technology with adaptive forming\/set\/reset schemes yielding down to 0.5 V with sensing time of 5 ns at 0.7 V","author":"jain","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","first-page":"478","article-title":"An N40 256K\n$\\times44$\n embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance","author":"chou","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","first-page":"246","article-title":"Envision: A 0.26-to-10 TOPS\/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI","author":"moons","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"},{"key":"ref20","first-page":"525","article-title":"XNOR-Net: ImageNet classification using binary convolutional neural networks","author":"rastegari","year":"2016","journal-title":"Proc Eur Conf Comput Vis (ECCV)"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2017.2732698"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2017.2697910"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref23","article-title":"Training high-performance and large-scale deep neural networks with full 8-bit integers","author":"yang","year":"2019","journal-title":"arXiv 1909 02384"},{"key":"ref26","first-page":"200","article-title":"A 4Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160 ns MLC-access capability","author":"sheu","year":"2011","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2017.00538"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/8919\/9049235\/8942647-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9049235\/08942647.pdf?arnumber=8942647","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T16:48:32Z","timestamp":1651078112000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8942647\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":30,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2019.2958568","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4]]}}}