{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T12:05:03Z","timestamp":1740139503449,"version":"3.37.3"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"TEXEO Project funded by the Spanish Research Plan","award":["TEC2016-80339-R"],"award-info":[{"award-number":["TEC2016-80339-R"]}]},{"name":"Madrid Community Research Project TAPIR-CM","award":["P2018\/TCS-4496"],"award-info":[{"award-number":["P2018\/TCS-4496"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2020,5]]},"DOI":"10.1109\/tcsi.2019.2961847","type":"journal-article","created":{"date-parts":[[2020,1,9]],"date-time":"2020-01-09T21:10:33Z","timestamp":1578604233000},"page":"1615-1626","source":"Crossref","is-referenced-by-count":6,"title":["Codes for Limited Magnitude Error Correction in Multilevel Cell Memories"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6226-2880","authenticated-orcid":false,"given":"Shanshan","family":"Liu","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2540-5234","authenticated-orcid":false,"given":"Pedro","family":"Reviriego","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3152-3245","authenticated-orcid":false,"given":"Fabrizio","family":"Lombardi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0390"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241871"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1063\/1.3524521"},{"journal-title":"Error Control Coding","year":"2004","author":"lin","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1002\/0471792748"},{"key":"ref14","first-page":"1648","article-title":"Interleaved parity check codes and reduced complexity detection","author":"wu","year":"2002","journal-title":"Proc IEEE Int Conf Commun"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"395","DOI":"10.1147\/rd.144.0395","article-title":"A class of optimal minimum odd-weight-column SEC-DED codes","volume":"14","author":"hsiao","year":"1970","journal-title":"IBM J Res Develop"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2047907"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.40"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081647"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2010.2040971"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1371\/journal.pone.0131964"},{"key":"ref4","first-page":"1","article-title":"Emerging memories technology landscape","author":"sandhu","year":"2014","journal-title":"Proc Non-Volatile Memory Technol Symp"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378664"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724687"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2016.7495263"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485960"},{"key":"ref5","first-page":"5615","article-title":"A high reliable design of memristor-based multilevel memory","author":"wang","year":"2015","journal-title":"Proc 34th Chin Control Conf"},{"journal-title":"Intel Optane Memory","year":"2019","key":"ref8"},{"journal-title":"Western Digital&#x2019;s HGST Division Creates New Phase-Change SSD that&#x2019;s Orders of Magnitude Faster than any NAND Flash Drive on the Market","year":"2014","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2013.285"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-017-01481-9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2018.3620975"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.67"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2018.8602848"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2019.8875283"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2019.2922631"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2346182"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2353992"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2014.6962060"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9080045\/08954897.pdf?arnumber=8954897","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T16:50:25Z","timestamp":1651078225000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8954897\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5]]},"references-count":30,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2019.2961847","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2020,5]]}}}