{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,9]],"date-time":"2026-05-09T17:15:51Z","timestamp":1778346951983,"version":"3.51.4"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61774038"],"award-info":[{"award-number":["61774038"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"China Major S&T Project","award":["2018ZX01031-101"],"award-info":[{"award-number":["2018ZX01031-101"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2020,11]]},"DOI":"10.1109\/tcsi.2020.3023157","type":"journal-article","created":{"date-parts":[[2020,9,22]],"date-time":"2020-09-22T23:47:25Z","timestamp":1600818445000},"page":"3933-3943","source":"Crossref","is-referenced-by-count":15,"title":["A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2645-9912","authenticated-orcid":false,"given":"Xinchao","family":"Shang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7227-3735","authenticated-orcid":false,"given":"Minyi","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chengjun","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yiming","family":"Xiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7232-7852","authenticated-orcid":false,"given":"Jiaming","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5520-1326","authenticated-orcid":false,"given":"Weiwei","family":"Shan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2018.8579321"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-018-9423-y"},{"key":"ref30","first-page":"1","article-title":"A 0.4 V 0.5fJ\/cycle TSPC flip-flop in 65nm LP CMOS with retention mode controlled by clock-gating cells","author":"moreau","year":"2019","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2333332"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2284364"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2418713"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417956"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2948164"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2893294"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.24"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2041845"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2165717"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2680433"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2959494"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2317137"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2857836"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079410"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2328658"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2220912"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2135550"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2717927"},{"key":"ref22","first-page":"2290","article-title":"Reliability enhancement of low-power sequential circuits using reconfigurable pulsed latches","volume":"61","author":"elsharkasy","year":"2014","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref21","first-page":"482","article-title":"Conditional push-pull pulsed latches with 726fJ.ps energy-delay product in 65nm CMOS","author":"consoli","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2735445"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2723020"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2252211"},{"key":"ref25","first-page":"1","article-title":"Timing-aware clock gating of pulsed-latch circuits for low power design","author":"yang","year":"2013","journal-title":"Proc Int Symp VLSI Design Autom Test (VLSI-DAT)"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9240118\/09204433.pdf?arnumber=9204433","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T16:48:57Z","timestamp":1651078137000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9204433\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11]]},"references-count":32,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2020.3023157","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,11]]}}}