{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,16]],"date-time":"2026-07-16T02:43:55Z","timestamp":1784169835169,"version":"3.55.0"},"reference-count":142,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","funder":[{"name":"Center for Brain-Inspired Computing one of six centers in Joint University Microelectronics Program JUMP"},{"name":"Semiconductor Research Corporation SRC program sponsored by Defense Advanced Research Projects Agency DARPA"},{"name":"National Science Foundation"},{"DOI":"10.13039\/100006234","name":"Sandia National Laboratories","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100006234","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Vannevar Bush Faculty Fellowship"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2021,6]]},"DOI":"10.1109\/tcsi.2021.3069682","type":"journal-article","created":{"date-parts":[[2021,4,6]],"date-time":"2021-04-06T19:48:16Z","timestamp":1617738496000},"page":"2281-2294","source":"Crossref","is-referenced-by-count":27,"title":["Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9999-9085","authenticated-orcid":false,"given":"Amogh","family":"Agrawal","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8815-2871","authenticated-orcid":false,"given":"Cheng","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8307-5785","authenticated-orcid":false,"given":"Tanvi","family":"Sharma","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0735-9695","authenticated-orcid":false,"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","first-page":"462","article-title":"A 90 nm 12 ns 32 Mb 2T1MTJ MRAM","author":"nebashi","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2239671"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2590142"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.92.088302"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614700"},{"key":"ref30","first-page":"27.2.1","article-title":"14 ns write speed 128 Mb density embedded STT-MRAM with endurance >1010 and 10yrs retention@85&#x00B0;C using novel low damage MTJ integration process","author":"sato","year":"2018","journal-title":"IEDM Tech Dig"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105369"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749716"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2022628"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.2965403"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547698"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2169456"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2568762"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/0304-8853(96)00062-5"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/srep29545"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1063\/1.1404125"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.54.9353"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304049"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2804"},{"key":"ref100","first-page":"1","article-title":"SOT-MRAM based analog in-memory computing for DNN inference","author":"doevenspeck","year":"2020","journal-title":"Proc IEEE Symp VLSI Technol"},{"key":"ref25","first-page":"1","article-title":"Physical origins and theoretical models of magnetic anisotropy","volume":"24","author":"bruno","year":"1993","journal-title":"Magnetismus von Festk&#x00F6;rpern und grenzfl&#x00E4;chen"},{"key":"ref50","article-title":"Sensor amplifier, memory device comprising same, and related method of operation","author":"seo","year":"2015"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2872584"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2166282"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2170778"},{"key":"ref57","first-page":"296","article-title":"A 45 nm 1 Mb embedded STT-MRAM with design techniques to minimize read-disturbance","author":"kim","year":"2011","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1147\/rd.501.0025"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842856"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9091403"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2925931"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006428"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2003029"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2481793"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228447"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547704"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2011.2124453"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3059031"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2235013"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2574939"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070050"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2011.6035047"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2960028"},{"key":"ref48","first-page":"424","article-title":"A 45 nm self-aligned-contact process 1 Gb NOR flash with 5 MB\/s program speed","author":"javanifard","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.3040425"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2011.5994447"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241773"},{"key":"ref44","article-title":"Resistive nonvolatile memory cells with shared access transistors","author":"jacob","year":"2020"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2013.6633792"},{"key":"ref127","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2013.102"},{"key":"ref126","doi-asserted-by":"publisher","DOI":"10.1038\/nmat3675"},{"key":"ref125","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.78.140403"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629936"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2015.2456510"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2018.2845890"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391540"},{"key":"ref128","doi-asserted-by":"publisher","DOI":"10.1038\/srep09400"},{"key":"ref70","first-page":"54","article-title":"STTRAM scaling and retention failure","volume":"17","author":"naeimi","year":"2013","journal-title":"Intel Technol J"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2279137"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1038\/nature14004"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479023"},{"key":"ref74","first-page":"1","article-title":"Improving STT-MRAM density through multibit error correction","author":"bel","year":"2014","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.49.090204"},{"key":"ref133","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2573836"},{"key":"ref134","doi-asserted-by":"publisher","DOI":"10.3390\/mi10050327"},{"key":"ref131","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2785"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1063\/1.4869828"},{"key":"ref132","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2008.406"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2007.4601218"},{"key":"ref136","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2020.2987211"},{"key":"ref135","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2867048"},{"key":"ref138","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2906932"},{"key":"ref137","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2774291"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2015.7273482"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.3003007"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2292055"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2712363"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865598"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2260365"},{"key":"ref140","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939682"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2536639"},{"key":"ref141","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3055830"},{"key":"ref66","article-title":"Resistive nonvolatile memory structure employing a statistical sensing scheme and method","author":"jacob","year":"2020"},{"key":"ref142","first-page":"163","article-title":"Reliability of 4 Mbit MRAM","author":"akerman","year":"2005","journal-title":"Proc IEEE Int Rel Phys Symp Proc 43rd Annu"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3020137"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2749522"},{"key":"ref2","first-page":"10","article-title":"1.1 computing&#x2019;s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2027907"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"ref109","doi-asserted-by":"publisher","DOI":"10.1063\/1.2976435"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0160-7"},{"key":"ref108","first-page":"1135","article-title":"Learning both weights and connections for efficient neural network","volume":"28","author":"han","year":"2015","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2016.84"},{"key":"ref107","article-title":"X-CHANGR: Changing memristive crossbar mapping for mitigating line-resistance induced accuracy degradation in deep neural networks","author":"agrawal","year":"2019","journal-title":"arXiv 1907 00285"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993513"},{"key":"ref106","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510653"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0099-8"},{"key":"ref105","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218688"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1038\/s41563-018-0137-y"},{"key":"ref104","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3000185"},{"key":"ref90","doi-asserted-by":"crossref","first-page":"1834","DOI":"10.1103\/PhysRevLett.83.1834","article-title":"Spin Hall effect","volume":"83","author":"hirsch","year":"1999","journal-title":"Phys Rev Lett"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref111","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614638"},{"key":"ref112","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927058"},{"key":"ref110","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2991679"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.1109\/INTMAG.2017.8008048"},{"key":"ref99","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-018-23886-2"},{"key":"ref96","first-page":"194t","article-title":"Manufacturable 300 mm platform solution for field-free switching SOT-MRAM","author":"garello","year":"2019","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2521712"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993516"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"},{"key":"ref14","author":"fleischer","year":"2018","journal-title":"Unlocking the Promise of Approximate Computing for On-Chip AI Acceleration"},{"key":"ref15","first-page":"280","article-title":"16.3 A 23 Mb\/s 23 pJ\/b fully synthesized true-random-number generator in 28 nm and 65 nm CMOS","author":"yang","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref118","doi-asserted-by":"publisher","DOI":"10.2307\/2322600"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"303","DOI":"10.1109\/JSSC.2015.2498601","article-title":"A 20 k-spin ising chip to solve combinatorial optimization problems with CMOS annealing","volume":"51","author":"yamaoka","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2014.2304683"},{"key":"ref117","article-title":"Stochastic spiking neural networks enabled by magnetic tunnel junctions: From nontelegraphic to telegraphic switching regimes","volume":"8","author":"liyanagedera","year":"2017","journal-title":"Phys Rev A Gen Phys"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3005413"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2297397"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1038\/srep44370"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2217514"},{"key":"ref119","author":"ausiello","year":"2012","journal-title":"Complexity and Approximation Combinatorial Optimization Problems and Their Approximability Properties"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCC.2019.00020"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2439733"},{"key":"ref114","doi-asserted-by":"publisher","DOI":"10.1109\/LMAG.2015.2496548"},{"key":"ref113","first-page":"5","article-title":"A magnetic tunnel junction based true random number generator with conditional perturb and real-time output probability tracking","author":"ho choi","year":"2014","journal-title":"IEDM Tech Dig"},{"key":"ref116","doi-asserted-by":"publisher","DOI":"10.1109\/LMAG.2017.2685358"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2023192"},{"key":"ref115","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevX.7.031014"},{"key":"ref120","first-page":"5","article-title":"Ising formulations of many NP problems","volume":"2","author":"lucas","year":"2014","journal-title":"Frontiers in Physiology"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2016.29"},{"key":"ref121","doi-asserted-by":"publisher","DOI":"10.1063\/1.4983636"},{"key":"ref122","doi-asserted-by":"crossref","first-page":"533","DOI":"10.1038\/323533a0","article-title":"Learning representations by back-propagating errors","volume":"323","author":"rumelhart","year":"1986","journal-title":"Nature"},{"key":"ref123","doi-asserted-by":"publisher","DOI":"10.3389\/fncom.2015.00099"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2018.8598290"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1038\/nature10309"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1126\/science.1218197"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1021\/acs.nanolett.6b01443"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9442414\/09395705.pdf?arnumber=9395705","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,14]],"date-time":"2021-10-14T00:53:32Z","timestamp":1634172812000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9395705\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6]]},"references-count":142,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2021.3069682","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,6]]}}}