{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T04:39:20Z","timestamp":1780634360440,"version":"3.54.1"},"reference-count":61,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","funder":[{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","award":["NSERCRGPIN-205034-2012052714"],"award-info":[{"award-number":["NSERCRGPIN-205034-2012052714"]}],"id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2021,8]]},"DOI":"10.1109\/tcsi.2021.3081917","type":"journal-article","created":{"date-parts":[[2021,5,27]],"date-time":"2021-05-27T22:36:52Z","timestamp":1622155012000},"page":"3265-3278","source":"Crossref","is-referenced-by-count":25,"title":["Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4282-5337","authenticated-orcid":false,"given":"Dhruv","family":"Patel","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Adam","family":"Neale","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Derek","family":"Wright","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8256-9828","authenticated-orcid":false,"given":"Manoj","family":"Sachdev","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2018.2794827"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2039949"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280732"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2498302"},{"key":"ref31","first-page":"1","article-title":"A current mode sense amplifier with self-compensation circuit for SRAM application","author":"xu","year":"2013","journal-title":"Proc of IEEE Int Conf on ASIC (ASICON)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/SubVT.2012.6404300"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/4.272089"},{"key":"ref36","first-page":"328","article-title":"A 65 nm CMOS comparator with modified latch to achieve 7 GHz\/1.3 mW at 1.2 V and 700 MHz\/47 $\\mu\\text{W}$\n at 0.6 V","author":"goll","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref35","first-page":"328","article-title":"A 65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy","author":"verma","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/SubVT.2012.6404299"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2899314"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2707392"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231284"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISVDAT.2015.7208082"},{"key":"ref29","first-page":"115","article-title":"A dynamic current-offset calibration (DCC) sense amplifier with fish-bone shaped bit-line (FBB) for high-density SRAMs","author":"takahashi","year":"1994","journal-title":"VLSI Symp Tech Dig"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1198687"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977312"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672006"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2010.0092"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.827566"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref23","first-page":"242","article-title":"A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28 nm CMOS","author":"giridhar","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/4.375969"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/4.245591"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2375824"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2117530"},{"key":"ref59","first-page":"824","article-title":"Architectural power models for SRAM and CAM structures based on hybrid analytical\/empirical techniques","author":"liang","year":"2007","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref58","first-page":"181","article-title":"A double-tail sense amplifier for low-voltage SRAM in 28 nm technology","author":"chiu","year":"2016","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref57","first-page":"318","article-title":"An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to $1.9\\times$\n reduction in energy\/access","author":"sinangil","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref56","author":"rabaey","year":"1996","journal-title":"Digital Integrated Circuits"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2014.6948970"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2563660"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2347707"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"ref10","first-page":"308","article-title":"5.6 Mb\/mm2 1R1W 8T SRAM arrays operating down to 560 mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14 nm FinFET CMOS technology","author":"keane","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.829399"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168967"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234387"},{"key":"ref13","first-page":"380","article-title":"A high-density 45nm SRAM using small-signal non-strobed regenerative sensing","author":"verma","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2001.912591"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055315"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/81.989159"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2268312"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609437"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1109\/TCSI.2009.2016182","article-title":"Criterion to evaluate input-offset voltage of a latch-type sense amplifier","volume":"57","author":"do","year":"2010","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref4","first-page":"226","article-title":"The scaling of data sensing schemes for high speed cache design in sub-$0.18~\\mu\\text{m}$\n technologies","author":"zhang","year":"2000","journal-title":"VLSI Symp Tech Dig"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.823443"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1989.48222"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405677"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.859510"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.911351"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.856280"},{"key":"ref9","first-page":"334","article-title":"A 6.2 GHz single ended current sense amplifier (CSA) based compileable 8T SRAM in 7 nm FinFET technology","author":"fritsch","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168937"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ICMIRA.2013.81"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803957"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818291"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2009.2013745"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2332260"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2013.6716525"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2011.6026649"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9481308\/09442830.pdf?arnumber=9442830","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T17:57:54Z","timestamp":1643219874000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9442830\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,8]]},"references-count":61,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2021.3081917","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,8]]}}}