{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,17]],"date-time":"2026-04-17T16:16:57Z","timestamp":1776442617620,"version":"3.51.2"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100001602","name":"Science Foundation Ireland","doi-asserted-by":"publisher","award":["14\/RP\/I2921"],"award-info":[{"award-number":["14\/RP\/I2921"]}],"id":[{"id":"10.13039\/501100001602","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Science and Technology Development Fund, Macau","award":["0044\/2019\/A1"],"award-info":[{"award-number":["0044\/2019\/A1"]}]},{"name":"Science and Technology Development Fund, Macau","award":["SKL-AMSV(UM)-2020-2022"],"award-info":[{"award-number":["SKL-AMSV(UM)-2020-2022"]}]},{"DOI":"10.13039\/501100004733","name":"University of Macau","doi-asserted-by":"publisher","award":["MYRG2018-00220-AMSV"],"award-info":[{"award-number":["MYRG2018-00220-AMSV"]}],"id":[{"id":"10.13039\/501100004733","id-type":"DOI","asserted-by":"publisher"}]},{"name":"National Science Center, Poland","award":["UMO-2017\/27\/B\/ST7\/01217"],"award-info":[{"award-number":["UMO-2017\/27\/B\/ST7\/01217"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2022,1]]},"DOI":"10.1109\/tcsi.2021.3094094","type":"journal-article","created":{"date-parts":[[2021,7,26]],"date-time":"2021-07-26T21:52:07Z","timestamp":1627336327000},"page":"51-63","source":"Crossref","is-referenced-by-count":30,"title":["A 529-\u03bcW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS"],"prefix":"10.1109","volume":"69","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2872-9421","authenticated-orcid":false,"given":"Peng","family":"Chen","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2320-5012","authenticated-orcid":false,"given":"Xi","family":"Meng","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4195-4551","authenticated-orcid":false,"given":"Jun","family":"Yin","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3579-8740","authenticated-orcid":false,"given":"Pui-In","family":"Mak","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2821-648X","authenticated-orcid":false,"given":"Rui P.","family":"Martins","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9848-1129","authenticated-orcid":false,"given":"Robert Bogdan","family":"Staszewski","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2551738"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2888874"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008472"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757387"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870440"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878836"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062978"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417963"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2314436"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385753"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2742518"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2359670"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1002\/0470041951"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2020.3039517"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596766"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2529004"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2017.8240224"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2577858"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596770"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2650782"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2414421"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939663"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/4.972142"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2273823"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642207"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2875099"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662516"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2019.8701844"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2004867"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ECCTD.2013.6662211"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2625462"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2936967"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1980.1094619"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310279"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2883397"},{"key":"ref36","volume-title":"All-digital-phase-locked-loop having a time-to-digital converter circuit with a dynamically adjustable offset delay","author":"Liu","year":"2015"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2682841"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2451915"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.889734"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/4.658619"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2015.7337735"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3009857"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2843337"},{"key":"ref44","article-title":"An ultra-low-power ADPLL for WPAN applications","author":"Chillara","year":"2013"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2625199"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9684154\/09493748.pdf?arnumber=9493748","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,11]],"date-time":"2024-01-11T22:37:30Z","timestamp":1705012650000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9493748\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1]]},"references-count":45,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2021.3094094","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,1]]}}}