{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:30:18Z","timestamp":1759332618256,"version":"3.37.3"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council (EPSRC) Programme under Functional Oxide Reconfigurable Technologies (FORTE) Grant","doi-asserted-by":"publisher","award":["EP\/R024642\/1"],"award-info":[{"award-number":["EP\/R024642\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]},{"name":"a SYnaptically connected brain-silicon Neural Closed-loop Hybrid system","award":["H2020-FETPROACT-2018-01"],"award-info":[{"award-number":["H2020-FETPROACT-2018-01"]}]},{"name":"RAEng Chair in Emerging Technologies","award":["CiET1819\/2\/93"],"award-info":[{"award-number":["CiET1819\/2\/93"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2021,12]]},"DOI":"10.1109\/tcsi.2021.3122381","type":"journal-article","created":{"date-parts":[[2021,11,2]],"date-time":"2021-11-02T21:30:38Z","timestamp":1635888638000},"page":"4876-4888","source":"Crossref","is-referenced-by-count":8,"title":["Design Flow for Hybrid CMOS\/Memristor Systems\u2014Part II: Circuit Schematics and Layout"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9192-2961","authenticated-orcid":false,"given":"Sachin","family":"Maheshwari","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0833-6209","authenticated-orcid":false,"given":"Spyros","family":"Stathopoulos","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2503-1001","authenticated-orcid":false,"given":"Jiaqi","family":"Wang","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8034-2398","authenticated-orcid":false,"given":"Alexander","family":"Serb","sequence":"additional","affiliation":[]},{"given":"Yihan","family":"Pan","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8997-1804","authenticated-orcid":false,"given":"Andrea","family":"Mifsud","sequence":"additional","affiliation":[]},{"given":"Lieuwe B.","family":"Leene","sequence":"additional","affiliation":[]},{"given":"Jiawei","family":"Shen","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8003-2146","authenticated-orcid":false,"given":"Christos","family":"Papavassiliou","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9778-1162","authenticated-orcid":false,"given":"Timothy G.","family":"Constandinou","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6267-6909","authenticated-orcid":false,"given":"Themistoklis","family":"Prodromakis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1038\/nmat2748"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1016\/j.mejo.2014.06.006"},{"key":"ref12","first-page":"1","article-title":"MRL&#x2014;Memristor ratioed logic","author":"kvatinsky","year":"2012","journal-title":"Proc Int Workshop Cell Nanoscale Netw Their Appl"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/NANOARCH.2010.5510933"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/JPROC.2011.2167489"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/TNANO.2013.2241075"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/CICC.2018.8357066"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1038\/s41563-019-0291-x"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/ISCAS.2018.8351192"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1016\/j.mejo.2012.10.001"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1038\/s41598-017-17785-1"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1109\/ISSCC19947.2020.9062979"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TNANO.2017.2691713"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1038\/s41586-020-1942-4"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.3389\/fnins.2021.651452"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.3389\/fnano.2021.633026"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/TVLSI.2013.2282132"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1038\/nature06932","article-title":"The missing memristor found","volume":"453","author":"strukov","year":"2008","journal-title":"Nature"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/ICSEE.2016.7806155"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/TCT.1971.1083337"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/IEDM.2015.7409720"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/TCSI.2021.3122343"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1038\/s41928-019-0270-x"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1038\/s41928-017-0002-z"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1038\/s41467-018-04624-8"},{"key":"ref26","article-title":"Memristive synapses are becoming reality","author":"laiho","year":"2010","journal-title":"The Neuromorphic Engineer"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/TCSI.2019.2940909"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9629436\/09598180.pdf?arnumber=9598180","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,3,8]],"date-time":"2022-03-08T21:36:29Z","timestamp":1646775389000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9598180\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12]]},"references-count":28,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2021.3122381","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2021,12]]}}}