{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T05:33:32Z","timestamp":1782970412669,"version":"3.54.5"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["U19A2074"],"award-info":[{"award-number":["U19A2074"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61904028"],"award-info":[{"award-number":["61904028"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2022,4]]},"DOI":"10.1109\/tcsi.2022.3140769","type":"journal-article","created":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T05:26:39Z","timestamp":1643174799000},"page":"1519-1531","source":"Crossref","is-referenced-by-count":67,"title":["Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell"],"prefix":"10.1109","volume":"69","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9794-8049","authenticated-orcid":false,"given":"Hao","family":"Cai","sequence":"first","affiliation":[{"name":"National ASIC System Engineering Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8507-8100","authenticated-orcid":false,"given":"Yanan","family":"Guo","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0894-1054","authenticated-orcid":false,"given":"Bo","family":"Liu","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5522-3899","authenticated-orcid":false,"given":"Mingyang","family":"Zhou","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9689-216X","authenticated-orcid":false,"given":"Juntong","family":"Chen","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9035-2189","authenticated-orcid":false,"given":"Xinning","family":"Liu","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8379-0321","authenticated-orcid":false,"given":"Jun","family":"Yang","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2015.29"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0092-2"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2362853"},{"key":"ref5","first-page":"224","article-title":"A 22 nm 1Mb 1024b-read and near-memory-computing dual-mode STT-MRAM macro with 42.6 GB\/s read bandwidth for security-aware mobile devices","volume-title":"IEEE ISSCC Dig. Tech. Papers","author":"Chang"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265099"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-021-3220-0"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2907063"},{"key":"ref9","first-page":"1","article-title":"Multi-pillar SOT-MRAM for accurate analog in-memory DNN inference","volume-title":"Proc. Symp. VLSI Technol.","author":"Doevenspeck"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0099-8"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2621344"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2858251"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3055830"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3059031"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3031290"},{"key":"ref18","first-page":"11","article-title":"A reflow-capable, embedded 8 Mb STT-MRAM macro with 9 nS read access time in 16 nm FinFET logic CMOS process","author":"Shih","year":"2020","journal-title":"IEDM Tech. Dig."},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510672"},{"key":"ref20","first-page":"2","article-title":"Manufacturable 22 nm FD-SOI embedded MRAM technology for industrial-grade MCU and IoT applications","author":"Naik","year":"2019","journal-title":"IEDM Tech. Dig."},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS51556.2021.9401723"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062953"},{"key":"ref23","first-page":"245","article-title":"A 22 nm 4 Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS\/W for tiny AI edge devices","volume-title":"IEEE ISSCC Dig. Tech. Papers","author":"Xue"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-020-16108-9"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-018-03140-z"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2020.2987211"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1002\/aelm.201800812"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3063719"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2951363"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2922889"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1063\/1.2198797"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1063\/1.1459605"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1038\/nmat1257"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/0375-9601(75)90174-7"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3061508"},{"key":"ref36","first-page":"252","article-title":"An 89 TOPS\/W and 16.3 TOPS\/mm 2 all-digital SRAM-based full-precision compute-in memory macro in 22 nm for machine-learning edge applications","volume-title":"IEEE ISSCC Dig. Tech. Papers","author":"Chih"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899730"},{"key":"ref38","first-page":"242","article-title":"A 351 TOPS\/W and 372.4 GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications","volume-title":"IEEE ISSCC Dig. Tech. Papers","author":"Dong"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365932"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702206"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3061260"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2906932"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2533438"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2014.07.019"},{"key":"ref45","volume-title":"Embedded Microprocessor Benchmark Consortium (EEMBC)","year":"2021"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9745276\/09678974.pdf?arnumber=9678974","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,13]],"date-time":"2024-01-13T22:19:30Z","timestamp":1705184370000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9678974\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4]]},"references-count":45,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2022.3140769","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,4]]}}}