{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T12:04:46Z","timestamp":1740139486887,"version":"3.37.3"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation (NSF) Center for Hardware and Embedded Systems Security and Trust","doi-asserted-by":"publisher","award":["1916722"],"award-info":[{"award-number":["1916722"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2022,7]]},"DOI":"10.1109\/tcsi.2022.3168420","type":"journal-article","created":{"date-parts":[[2022,4,28]],"date-time":"2022-04-28T19:54:21Z","timestamp":1651175661000},"page":"2906-2915","source":"Crossref","is-referenced-by-count":0,"title":["THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs"],"prefix":"10.1109","volume":"69","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6074-535X","authenticated-orcid":false,"given":"John M.","family":"Emmert","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of Cincinnati, Cincinnati, OH, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anvesh K.","family":"Perumalla","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of Cincinnati, Cincinnati, OH, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5594-4103","authenticated-orcid":false,"given":"Tristan J.","family":"Hudson","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of Cincinnati, Cincinnati, OH, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luis M.","family":"Concha","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of Cincinnati, Cincinnati, OH, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2002.1000311"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45238-6_12"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST47458.2019.9006690"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS48704.2020.9184563"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/NAECON46414.2019.9057912"},{"volume-title":"Systems and methods for asynchronous programmable gate array devices","year":"2020","author":"Emmert","key":"ref7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.7"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2334493"},{"key":"ref10","first-page":"117","article-title":"MOLES: Malicious off-chip leakage enabled by side-channels","volume-title":"IEEE\/ACM Int. Conf. Comput.-Aided Design-Dig. Tech. Papers","author":"Lin"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1992.270231"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.1996.542821"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/5.362752"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2413759"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2413757"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/71317.1186643"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2000.836983"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2003.12.004"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.1997.662351"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1992.591107"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776031"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2014.6855561"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.261"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140229"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2742-8"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/5.231340"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-79800-9"},{"volume-title":"NCSU Cadence Design Kit","key":"ref32"},{"volume-title":"NCSU FreePDK45","key":"ref33"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968300"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ATC.2009.5349341"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46117-5_6"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"volume-title":"OpenCores","key":"ref38"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-63465-7_226"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2021.3051334"},{"article-title":"An open source design flow for asynchronous circuits","volume-title":"Proc. Government Microcircuit Appl. Crit. Technol. Conf. (GOMACTech)","author":"Manohar","key":"ref41"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/8919\/9809931\/9764890-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9809931\/09764890.pdf?arnumber=9764890","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,22]],"date-time":"2024-01-22T21:58:19Z","timestamp":1705960699000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9764890\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7]]},"references-count":39,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2022.3168420","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2022,7]]}}}