{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,17]],"date-time":"2026-07-17T23:13:53Z","timestamp":1784330033017,"version":"3.55.0"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2022,10,1]],"date-time":"2022-10-01T00:00:00Z","timestamp":1664582400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,10,1]],"date-time":"2022-10-01T00:00:00Z","timestamp":1664582400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,1]],"date-time":"2022-10-01T00:00:00Z","timestamp":1664582400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"German Research Foundation (DFG) Project \u201cACCROSS\u201d","award":["HE 2343\/16-1"],"award-info":[{"award-number":["HE 2343\/16-1"]}]},{"name":"German Research Foundation (DFG) Project \u201cACCROSS\u201d","award":["AM 534\/3-1"],"award-info":[{"award-number":["AM 534\/3-1"]}]},{"name":"German Research Foundation (DFG) Project \u201cACCROSS\u201d","award":["428566201"],"award-info":[{"award-number":["428566201"]}]},{"name":"\u201cSERRANO\u201d","award":["101017168"],"award-info":[{"award-number":["101017168"]}]},{"name":"Advantest as part of the Graduate School \u201cIntelligent Methods for Test and Reliability\u201d (GS-IMTR), University of Stuttgart"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2022,10]]},"DOI":"10.1109\/tcsi.2022.3183858","type":"journal-article","created":{"date-parts":[[2022,6,23]],"date-time":"2022-06-23T19:33:02Z","timestamp":1656012782000},"page":"4141-4153","source":"Crossref","is-referenced-by-count":6,"title":["Variability-Aware Approximate Circuit Synthesis via Genetic Optimization"],"prefix":"10.1109","volume":"69","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2886-6896","authenticated-orcid":false,"given":"Konstantinos","family":"Balaskas","sequence":"first","affiliation":[{"name":"Department of Physics, Aristotle University of Thessaloniki, Thessaloniki, Greece"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0148-0523","authenticated-orcid":false,"given":"Florian","family":"Klemme","sequence":"additional","affiliation":[{"name":"Chair for Semiconductor Test and Reliability (STAR), University of Stuttgart, Stuttgart, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8110-7122","authenticated-orcid":false,"given":"Georgios","family":"Zervakis","sequence":"additional","affiliation":[{"name":"Chair for Embedded Systems, Karlsruhe Institute of Technology, Karlsruhe, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0285-2202","authenticated-orcid":false,"given":"Kostas","family":"Siozios","sequence":"additional","affiliation":[{"name":"Department of Physics, Aristotle University of Thessaloniki, Thessaloniki, Greece"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5649-3102","authenticated-orcid":false,"given":"Hussam","family":"Amrouch","sequence":"additional","affiliation":[{"name":"Chair for Semiconductor Test and Reliability (STAR), University of Stuttgart, Stuttgart, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9602-2922","authenticated-orcid":false,"given":"Jorg","family":"Henkel","sequence":"additional","affiliation":[{"name":"Chair for Embedded Systems, Karlsruhe Institute of Technology, Karlsruhe, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.131"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784500"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714942"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3106149"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00039"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2898006"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2981395"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2015.7493153"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2682885"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3386263.3406926"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3177864"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2018.8644828"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-019-05772-5"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2020.2987946"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3103200"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2717790"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062331"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2969462"},{"key":"ref20","volume-title":"Synopsys EDA Tools","year":"2021"},{"key":"ref21","first-page":"3","article-title":"A 14 nm logic technology featuring $2^{\\textrm{nd}}$\n-generation FinFET, air-gapped interconnects, self-aligned double patterning and a $0.0588~\\mu\\text{m}^{2}$\n SRAM cell size","volume-title":"IEDM Tech. Dig.","author":"Natarajan"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2015.7313862"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2990672"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717783"},{"key":"ref25","volume-title":"Silvaco Open Source Library","year":"2019"},{"key":"ref26","volume-title":"SiliconSmart","year":"2017"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2657799"},{"key":"ref28","first-page":"612","article-title":"Approximation through logic isolation for the design of quality configurable circuits","volume-title":"Proc. Design, Autom. Test Eur. Conf. Exhib. (DATE)","author":"Jain"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2308214"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1504\/IJOR.2014.064541"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/4235.996017"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2900160"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3058451"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-99322-5_10"},{"key":"ref35","volume-title":"UCI machine learning repository","author":"Dua","year":"2017"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465702"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2015.7112763"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9904939\/09804695.pdf?arnumber=9804695","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T04:34:22Z","timestamp":1706762062000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9804695\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10]]},"references-count":37,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2022.3183858","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,10]]}}}