{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T23:46:28Z","timestamp":1780443988556,"version":"3.54.1"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"National Research Foundation funded by the Korea Ministry of Science and Information & Communication Technology","award":["2019R1A5A1027055"],"award-info":[{"award-number":["2019R1A5A1027055"]}]},{"DOI":"10.13039\/501100003836","name":"IC Design Education Center","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1109\/tcsi.2022.3222862","type":"journal-article","created":{"date-parts":[[2022,11,24]],"date-time":"2022-11-24T18:27:29Z","timestamp":1669314449000},"page":"772-782","source":"Crossref","is-referenced-by-count":3,"title":["Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8532-1385","authenticated-orcid":false,"given":"Han-Gyeol","family":"Mun","sequence":"first","affiliation":[{"name":"Department of Convergence IT Engineering, Pohang University of Science and Technology, Pohang, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0027-2666","authenticated-orcid":false,"given":"Seunghyun","family":"Moon","sequence":"additional","affiliation":[{"name":"Department of Convergence IT Engineering, Pohang University of Science and Technology, Pohang, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5453-0793","authenticated-orcid":false,"given":"Byungjun","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Pohang, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7002-5973","authenticated-orcid":false,"given":"Kyeong-Jun","family":"Lee","sequence":"additional","affiliation":[{"name":"Department of Convergence IT Engineering, Pohang University of Science and Technology, Pohang, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1814-6211","authenticated-orcid":false,"given":"Jae-Yoon","family":"Sim","sequence":"additional","affiliation":[{"name":"Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Pohang, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2869150"},{"key":"ref2","article-title":"Revisiting ResNets: Improved training and scaling strategies","author":"Bello","year":"2021","journal-title":"arXiv:2103.07579"},{"key":"ref3","article-title":"High-performance large-scale image recognition without normalization","author":"Brock","year":"2021","journal-title":"arXiv:2102.06171"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3066883"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310400"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001177"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.195"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"ref11","article-title":"Analog computation in flash memory for datacenter-scale AI inference in a small chip","volume-title":"Proc. Hot Chips","author":"Fick"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2018.8445101"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT52863.2021.9609919"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2022.3170152"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2019.00140"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00745"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00091"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731757"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3099034"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC53895.2021.9634838"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063111"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365943"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2019.00042"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-58539-6_26"},{"key":"ref26","volume-title":"Automatic differentiation in pytorch","author":"Paszke","year":"2017"},{"key":"ref27","article-title":"SCALE-sim: Systolic CNN accelerator simulator","author":"Samajdar","year":"2018","journal-title":"arXiv:1811.02883"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00474"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9473985"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2019.2929696"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.4324\/9781410605337-29"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2019.00293"},{"key":"ref33","article-title":"EfficientNet: Rethinking model scaling for convolutional neural networks","author":"Tan","year":"2019","journal-title":"arXiv:1905.11946"},{"key":"ref34","article-title":"EfficientNetV2: Smaller models and faster training","author":"Tan","year":"2021","journal-title":"arXiv:2104.00298"},{"key":"ref35","author":"Wightman","year":"2019","journal-title":"Pytorch Image Models"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00030"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474145"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/10027800\/09961910.pdf?arnumber=9961910","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T02:46:40Z","timestamp":1706755600000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9961910\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2]]},"references-count":37,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2022.3222862","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,2]]}}}