{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T15:20:39Z","timestamp":1783610439912,"version":"3.55.0"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2023,5,1]],"date-time":"2023-05-01T00:00:00Z","timestamp":1682899200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,5,1]],"date-time":"2023-05-01T00:00:00Z","timestamp":1682899200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,5,1]],"date-time":"2023-05-01T00:00:00Z","timestamp":1682899200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2020YFB2205502"],"award-info":[{"award-number":["2020YFB2205502"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"Joint Funds of the National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["U20A20204"],"award-info":[{"award-number":["U20A20204"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100013314","name":"111 Project","doi-asserted-by":"publisher","award":["B18001"],"award-info":[{"award-number":["B18001"]}],"id":[{"id":"10.13039\/501100013314","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2023,5]]},"DOI":"10.1109\/tcsi.2023.3244338","type":"journal-article","created":{"date-parts":[[2023,2,14]],"date-time":"2023-02-14T18:57:44Z","timestamp":1676401064000},"page":"1835-1845","source":"Crossref","is-referenced-by-count":31,"title":["A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6296-1905","authenticated-orcid":false,"given":"Jiahao","family":"Song","sequence":"first","affiliation":[{"name":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2181-9042","authenticated-orcid":false,"given":"Xiyuan","family":"Tang","sequence":"additional","affiliation":[{"name":"Center for Brain Inspired Chips, Institute for Artificial Intelligence, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1438-2348","authenticated-orcid":false,"given":"Xin","family":"Qiao","sequence":"additional","affiliation":[{"name":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4951-4286","authenticated-orcid":false,"given":"Yuan","family":"Wang","sequence":"additional","affiliation":[{"name":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7514-0767","authenticated-orcid":false,"given":"Runsheng","family":"Wang","sequence":"additional","affiliation":[{"name":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ru","family":"Huang","sequence":"additional","affiliation":[{"name":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref13","first-page":"1","article-title":"A 16 Kb transpose 6T SRAM in-memory-computing macro based on robust charge-domain computing","author":"song","year":"2021","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref12","article-title":"Training and inference with integers in deep neural networks","author":"wu","year":"2018","journal-title":"arXiv 1802 04680"},{"key":"ref15","first-page":"252","article-title":"An 89 TOPS\/W and 16.3 TOPS\/mm2 all-digital SRAM-based full-precision compute-in memory macro in 22 nm for machine-learning edge applications","volume":"64","author":"chih","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2922889"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3064189"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3186024"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3061260"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702715"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731754"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3061508"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662435"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3092759"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3165352"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3168053"},{"key":"ref46","first-page":"1","article-title":"A 40-nm, 2M-cell, 8b-precision, hybrid SLC-MLC PCM computing-in-memory macro with 20.5&#x2013;65.0 TOPS\/W for tiny-AI edge devices","volume":"65","author":"khwa","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3036209"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731715"},{"key":"ref47","first-page":"178","article-title":"A 22 nm 4 Mb STT-MRAM data-encrypted near-memory computation macro with a 192 GB\/s read-and-decryption bandwidth and 25.1&#x2013;55.1 TOPS\/W 8b MAC for AI operations","volume":"65","author":"chiu","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731545"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772789"},{"key":"ref44","first-page":"240","article-title":"A 65 nm 3T dynamic analog RAM-based computing-in-memory macro and CNN accelerator with retention enhancement, adaptive analog sparsity and 44 TOPS\/W system energy efficiency","volume":"64","author":"chen","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365932"},{"key":"ref49","first-page":"1","article-title":"A 40 nm 64 kb 26.56 TOPS\/W 2.37 Mb\/mm2 RRAM binary\/compute-in-memory macro with 4.23&#x00D7; improvement in density and75% use of sensing dynamic range","volume":"65","author":"spetalnick","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC56115.2022.9980672"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062949"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2980533"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-021-3234-0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365958"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492476"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492347"},{"key":"ref40","first-page":"1","article-title":"A 28 nm 1 Mb time-domain computing-in-memory 6T-SRAM macro with a 6.6 ns latency, 1241 GOPS and 37.01 TOPS\/W for 8b-MAC operations for edge-AI devices","volume":"65","author":"wu","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772821"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772826"},{"key":"ref37","first-page":"246","article-title":"A 28 nm 64 Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips","author":"si","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310397"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2992886"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2987714"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492403"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492444"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365788"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3095232"},{"key":"ref39","first-page":"250","article-title":"A 28 nm 384 kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips","volume":"64","author":"su","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3056447"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3152653"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2782087"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3080042"},{"key":"ref22","first-page":"248c","article-title":"A ternary based bit scalable, 8.80 TOPS\/W CNN accelerator with many-core processing-in-memory architecture with 896 K synapses\/mm2","author":"okumura","year":"2019","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778160"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062985"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075883"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899730"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/10109891\/10044587.pdf?arnumber=10044587","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,15]],"date-time":"2023-05-15T19:03:12Z","timestamp":1684177392000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10044587\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,5]]},"references-count":54,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2023.3244338","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,5]]}}}