{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,25]],"date-time":"2026-02-25T16:58:13Z","timestamp":1772038693949,"version":"3.50.1"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2023,6,1]],"date-time":"2023-06-01T00:00:00Z","timestamp":1685577600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,6,1]],"date-time":"2023-06-01T00:00:00Z","timestamp":1685577600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,6,1]],"date-time":"2023-06-01T00:00:00Z","timestamp":1685577600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000780","name":"European Commission Horizon 2020 Framework through The European Pilot project","doi-asserted-by":"publisher","award":["101034126"],"award-info":[{"award-number":["101034126"]}],"id":[{"id":"10.13039\/501100000780","id-type":"DOI","asserted-by":"publisher"}]},{"name":"WiPLASH project","award":["863337"],"award-info":[{"award-number":["863337"]}]},{"name":"CSEL Joint Undertaking Horizon 2020 through the AI4DI","award":["826060"],"award-info":[{"award-number":["826060"]}]},{"name":"GreenWaves Technologies"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2023,6]]},"DOI":"10.1109\/tcsi.2023.3254810","type":"journal-article","created":{"date-parts":[[2023,3,15]],"date-time":"2023-03-15T17:54:13Z","timestamp":1678902853000},"page":"2450-2463","source":"Crossref","is-referenced-by-count":24,"title":["Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0041-7917","authenticated-orcid":false,"given":"Gianmarco","family":"Ottavi","sequence":"first","affiliation":[{"name":"Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Bologna, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7495-6895","authenticated-orcid":false,"given":"Angelo","family":"Garofalo","sequence":"additional","affiliation":[{"name":"Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Bologna, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9221-4633","authenticated-orcid":false,"given":"Giuseppe","family":"Tagliavini","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering (DISI), University of Bologna, Bologna, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7924-933X","authenticated-orcid":false,"given":"Francesco","family":"Conti","sequence":"additional","affiliation":[{"name":"Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Bologna, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6688-1603","authenticated-orcid":false,"given":"Alfio Di","family":"Mauro","sequence":"additional","affiliation":[{"name":"IIS Integrated Systems Laboratory, ETH Züric, Züric, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8068-3806","authenticated-orcid":false,"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Bologna, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0651-5393","authenticated-orcid":false,"given":"Davide","family":"Rossi","sequence":"additional","affiliation":[{"name":"Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Bologna, Italy"}]}],"member":"263","reference":[{"key":"ref13","article-title":"Mixed precision quantization of ConvNets via differentiable neural architecture search","author":"wu","year":"2018","journal-title":"arXiv 1812 00090"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2019.00881"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2912307"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2019.00038"},{"key":"ref14","article-title":"On periodic functions as regularizers for quantization of neural networks","author":"naumov","year":"2018","journal-title":"arXiv 1811 09862"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2983648"},{"key":"ref30","article-title":"MLPerf tiny benchmark","author":"banbury","year":"2021","journal-title":"arXiv 2106 07597"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00474"},{"key":"ref33","first-page":"1","article-title":"SamurAI: A 1.7MOPS-36GOPS adaptive versatile IoT node with 15,000? peak-to-idle power reduction, 207ns wake-up time and 1.3TOPS\/W ML efficiency","author":"miro-panades","year":"2020","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref10","article-title":"MobileNets: Efficient convolutional neural networks for mobile vision applications","author":"howard","year":"2017","journal-title":"arXiv 1704 04861"},{"key":"ref32","doi-asserted-by":"crossref","first-page":"2256","DOI":"10.1109\/JSSC.2021.3056219","article-title":"SleepRunner: A 28-nm FDSOI ULP cortex-M0 MCU with ULL SRAM and UFBR PVT compensation for 2.6–3.6-? W\/DMIPS 40–80-MHz active mode and 131-nW\/kB fully retentive deep-sleep mode","volume":"56","author":"bol","year":"2021","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR42600.2020.00242"},{"key":"ref1","article-title":"Bayesian bits: Unifying quantization and pruning","author":"van baalen","year":"2020","journal-title":"arXiv 2005 07093"},{"key":"ref17","first-page":"11875","article-title":"HAWQ-V3: Dyadic neural network quantization","author":"yao","year":"2021","journal-title":"Proc Int Conf Mach Learn"},{"key":"ref16","first-page":"18518","article-title":"HAWQ-V2: Hessian aware trace-weighted quantization of neural networks","volume":"33","author":"dong","year":"2020","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref19","first-page":"246","article-title":"14.5 Envision: A 0.26-to-10TOPS\/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28nm FDSOI","author":"moons","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref18","article-title":"Bridging the accuracy gap for 2-bit quantized neural networks (QNN)","author":"choi","year":"2018","journal-title":"arXiv 1807 06964"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3114881"},{"key":"ref23","year":"2020","journal-title":"Lattice sensAI Delivers 10X Performance Boost for Low-Power Smart IoT Devices at the Edge"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474087"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.090"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008534"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465915"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2010.5548579"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176639"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3028691"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2021.3072337"},{"key":"ref7","year":"2022","journal-title":"ARM Helium"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3387902.3394038"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310262"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062989"},{"key":"ref6","article-title":"CMSIS-NN: Efficient neural network kernels for arm Cortex-M CPUs","author":"lai","year":"2018","journal-title":"arXiv 1801 06601 [cs]"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1098\/rsta.2019.0155"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/10137339\/10071725.pdf?arnumber=10071725","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,12]],"date-time":"2023-06-12T18:33:04Z","timestamp":1686594784000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10071725\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6]]},"references-count":34,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2023.3254810","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,6]]}}}