{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:21:49Z","timestamp":1772119309526,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2023,7,1]],"date-time":"2023-07-01T00:00:00Z","timestamp":1688169600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,7,1]],"date-time":"2023-07-01T00:00:00Z","timestamp":1688169600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,7,1]],"date-time":"2023-07-01T00:00:00Z","timestamp":1688169600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Institute of Information and Communications Technology Planning and Evaluation (IITP) Grant through the Korea Government (MSIT)","award":["2022-0-01171"],"award-info":[{"award-number":["2022-0-01171"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2023,7]]},"DOI":"10.1109\/tcsi.2023.3272626","type":"journal-article","created":{"date-parts":[[2023,5,15]],"date-time":"2023-05-15T18:33:35Z","timestamp":1684175615000},"page":"2734-2743","source":"Crossref","is-referenced-by-count":6,"title":["A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0594-4206","authenticated-orcid":false,"given":"Yoonjae","family":"Choi","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]},{"given":"Hyunsu","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Semiconductor System Engineering, Korea University, Seoul, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9545-9196","authenticated-orcid":false,"given":"Jonghyuck","family":"Choi","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8247-6277","authenticated-orcid":false,"given":"Jincheol","family":"Sim","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]},{"given":"Youngwook","family":"Kwon","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]},{"given":"Seungwoo","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Semiconductor System Engineering, Korea University, Seoul, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-6748-1283","authenticated-orcid":false,"given":"Changmin","family":"Sim","sequence":"additional","affiliation":[{"name":"Department of Semiconductor System Engineering, Korea University, Seoul, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4379-7905","authenticated-orcid":false,"given":"Chulwoo","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3065462"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2511157"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870304"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2940332"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3143468"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"821","DOI":"10.1109\/JSSC.2016.2519391","article-title":"A bang bang phase-locked loop using automatic loop gain control and loop latency reduction techniques","volume":"51","author":"kuan","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref11","first-page":"328","article-title":"19.4 A 0.0049 mm2 2.3 GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving–236.2dB jitter-FOM","author":"chuang","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3210212"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2788876"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3200475"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3148174"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.876206"},{"key":"ref17","first-page":"268","article-title":"A sub-sampling all-digital fractional-N frequency synthesizer with–111 dBc\/Hz in-band phase noise and an FOM of–242 dB","author":"chen","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2546304"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2918940"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2936765"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/4.192044"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.826317"},{"key":"ref26","first-page":"314","article-title":"A double-tail latch-type voltage sense amplifier with 18ps setup+hold time","author":"schinkel","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.875308"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2082272"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2013.6569537"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857359"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1982.1056489"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2010.5716609"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2959252"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref7","first-page":"117","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref9","first-page":"390","article-title":"25.6 A 5.25GHz subsampling PLL with a VCO-phase-noise suppression technique","author":"ting","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3045168"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731636"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3005780"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3038818"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/10164683\/10124649.pdf?arnumber=10124649","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,17]],"date-time":"2023-07-17T18:03:04Z","timestamp":1689616984000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10124649\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7]]},"references-count":33,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2023.3272626","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,7]]}}}