{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T16:07:03Z","timestamp":1780675623575,"version":"3.54.1"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100024250","name":"Israel Innovation Authority through the GenPro Magnet Program","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100024250","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2024,1]]},"DOI":"10.1109\/tcsi.2023.3323425","type":"journal-article","created":{"date-parts":[[2023,10,23]],"date-time":"2023-10-23T18:39:05Z","timestamp":1698086345000},"page":"223-236","source":"Crossref","is-referenced-by-count":19,"title":["HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems"],"prefix":"10.1109","volume":"71","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-3377-6529","authenticated-orcid":false,"given":"Yehuda","family":"Kra","sequence":"first","affiliation":[{"name":"Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-7124-6437","authenticated-orcid":false,"given":"Yonatan","family":"Shoshan","sequence":"additional","affiliation":[{"name":"Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8745-2688","authenticated-orcid":false,"given":"Yehuda","family":"Rudin","sequence":"additional","affiliation":[{"name":"Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8233-4711","authenticated-orcid":false,"given":"Adam","family":"Teman","sequence":"additional","affiliation":[{"name":"Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/1971\/1\/012100"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522302"},{"key":"ref3","volume-title":"Instruction sets should be free: The case for RISC-V","author":"Asanovi\u0107","year":"2014"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942056"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"ref6","volume-title":"PicoRV32\u2014A Size-Optimized RISC-V CPU","author":"Wolf","year":"2015"},{"key":"ref7","volume-title":"SweRV Core From Western Digital","year":"2019"},{"key":"ref8","volume-title":"Ibex RISC-V Core","year":"2017"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2017.8106976"},{"key":"ref10","volume-title":"biRISC-V: 32-Bit Superscalar RISC-V CPU (by Ultraembedded)","year":"2021"},{"key":"ref11","volume-title":"The Berkeley out-of-order machine (BOOM): An industry-competitive, synthesizable, parameterized RISC-V processor","author":"Asanovic","year":"2015"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2016.130"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926114"},{"key":"ref14","volume-title":"CVA6 RISC-V CPU","year":"2020"},{"key":"ref15","volume-title":"The Rocket chip generator","volume":"4","author":"Asanovic","year":"2016"},{"key":"ref16","volume-title":"Z-scale: Tiny 32-bit RISC-V systems","author":"Lee"},{"key":"ref17","article-title":"Design of energy-efficient RISC-V-based edge-computing devices","author":"Schiavone","year":"2020"},{"key":"ref18","volume-title":"The PULP Platform","author":"Benini","year":"2015"},{"key":"ref19","volume-title":"OpenHW Group CORE-V CV32E40P RISC-V IP","year":"2020"},{"key":"ref20","volume-title":"GreenWaves Technologies\u2014Low Power Cores","year":"2023"},{"key":"ref21","volume-title":"Who Uses PULP?","year":"2023"},{"key":"ref22","volume-title":"PULP RISC-V GNU Toolchain","year":"2020"},{"key":"ref23","volume-title":"CoreMark","year":"2009"},{"key":"ref24","volume-title":"Embench: A Modern Embedded Benchmark Suite","year":"2015"},{"key":"ref25","volume-title":"Computer Organization and Design RISC-V Edition: The Hardware Software Interface","author":"Patterson","year":"2020"},{"key":"ref26","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy","year":"2017"},{"key":"ref27","volume-title":"SiFive e76","year":"2022"},{"key":"ref28","first-page":"1","article-title":"Design and implementation of a RISC-V ISA-based in-order dual issue superscalar processor","volume-title":"Proc. RISC-V Summit","author":"Libin"},{"key":"ref29","volume-title":"SweRV cores roadmap","author":"Bandic"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.05.007"},{"key":"ref31","volume-title":"Open On-Chip Debugger (OpenOCD)","author":"Rath","year":"2021"},{"key":"ref32","volume-title":"FreeRTOS\u2014Real-Time Operating System for Microcontrollers","author":"Barry","year":"2003"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS46596.2019.8965067"},{"key":"ref34","volume-title":"From swift to mighty: A cost-benefit analysis of ibex and CV32E40P regarding application performance, power and area","author":"Gallmann"},{"key":"ref35","volume-title":"CoreMark Scores on WikiChip","year":"2021"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS48785.2022.9937866"},{"key":"ref37","article-title":"GreenRio: A modern RISC-V microprocessor completely designed with a open-source EDA flow","volume-title":"Proc. Workshop Open-Source EDA Technol. (WOSET)","author":"Zhu"},{"key":"ref38","volume-title":"Embench Results Repository","author":"Bennet","year":"2021"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.3390\/mi12030292"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3318301"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067643"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2021.3072337"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/10391078\/10289711.pdf?arnumber=10289711","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,18]],"date-time":"2024-01-18T01:22:07Z","timestamp":1705540927000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10289711\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1]]},"references-count":42,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2023.3323425","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,1]]}}}