{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T04:07:14Z","timestamp":1781237234557,"version":"3.54.1"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2024,3,1]],"date-time":"2024-03-01T00:00:00Z","timestamp":1709251200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,3,1]],"date-time":"2024-03-01T00:00:00Z","timestamp":1709251200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,3,1]],"date-time":"2024-03-01T00:00:00Z","timestamp":1709251200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003052","name":"Technology Innovation Program (or Industrial Strategic Technology Development Program","doi-asserted-by":"publisher","award":["20014490"],"award-info":[{"award-number":["20014490"]}],"id":[{"id":"10.13039\/501100003052","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Development of Technology for Commercializing Lv.4 Self-driving Computing Platform Based on Centralized Architecture)"},{"DOI":"10.13039\/501100003052","name":"Ministry of Trade, Industry and Energy","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003052","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Institute of Information and communications Technology Planning and Evaluation"},{"DOI":"10.13039\/501100003621","name":"Korea Government (MSIT)","doi-asserted-by":"publisher","award":["2021-0-00106"],"award-info":[{"award-number":["2021-0-00106"]}],"id":[{"id":"10.13039\/501100003621","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2024,3]]},"DOI":"10.1109\/tcsi.2023.3335949","type":"journal-article","created":{"date-parts":[[2023,12,14]],"date-time":"2023-12-14T20:05:10Z","timestamp":1702584310000},"page":"1158-1171","source":"Crossref","is-referenced-by-count":42,"title":["A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and Dataflow"],"prefix":"10.1109","volume":"71","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4506-7930","authenticated-orcid":false,"given":"Minsik","family":"Kim","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Computer Sciences, Univeristy of Michigan, Ann Arbor, MI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kyoungseok","family":"Oh","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-4091-6907","authenticated-orcid":false,"given":"Youngmock","family":"Cho","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-3485-9960","authenticated-orcid":false,"given":"Hojin","family":"Seo","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7527-6971","authenticated-orcid":false,"given":"Xuan Truong","family":"Nguyen","sequence":"additional","affiliation":[{"name":"Department of Next-generation Semiconductor Convergence and Open Sharing System (COSS), Seoul National University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6811-9647","authenticated-orcid":false,"given":"Hyuk-Jae","family":"Lee","sequence":"additional","affiliation":[{"name":"Inter-University Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3434398"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TITS.2019.2892405"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.3390\/app12083826"},{"key":"ref4","article-title":"YOLOv3: An incremental improvement","author":"Redmon","year":"2018","journal-title":"arXiv:1804.02767"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.2004.10934"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR42600.2020.01079"},{"key":"ref7","volume-title":"NVIDIA Jetson Nano","year":"2023"},{"key":"ref8","volume-title":"NVIDIA Xavier NX","year":"2023"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-44534-8_25"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3120629"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3508546.3508576"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9180843"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2020.3020569"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3153288"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.91"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICACCS48705.2020.9074315"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/WACV51458.2022.00138"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TITS.2022.3158253"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530576"},{"key":"ref20","volume-title":"NVIDIA Geforce RTX 2080Ti","year":"2023"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.3390\/cryptography6020016"},{"key":"ref22","article-title":"A white paper on neural network quantization","author":"Nagel","year":"2021","journal-title":"arXiv:2106.08295"},{"key":"ref23","article-title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and Huffman coding","author":"Han","year":"2015","journal-title":"arXiv:1510.00149"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2018.2883087"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293904"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2018.2864321"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2905242"},{"key":"ref29","volume-title":"Digilent Nexys A7 100T","year":"2023"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3151916"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783725"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2016.2592330"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001177"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3198246"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00286"},{"key":"ref36","author":"Fu","year":"2017","journal-title":"Deep Learning with INT8 Optimization on Xilinx Devices"},{"key":"ref37","article-title":"MCUNetV2: Memory-efficient patch-based inference for tiny deep learning","author":"Lin","year":"2021","journal-title":"arXiv:2110.15352"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR46437.2021.01283"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/PAAP54281.2021.9720468"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.3390\/mi13111983"},{"key":"ref41","volume-title":"Avnet ZedBoard","year":"2023"},{"key":"ref42","volume-title":"AMD Zynq 7000 SoC ZC702 Evaluation Kit","year":"2023"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52729.2023.00721"},{"key":"ref44","volume-title":"Ultralytics YOLOv8","year":"2023"},{"key":"ref45","volume-title":"NVIDIA V100 Tensor Core GPU","year":"2023"},{"key":"ref46","volume-title":"Jetson Modules","year":"2023"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/10449955\/10360333.pdf?arnumber=10360333","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,20]],"date-time":"2024-12-20T19:15:14Z","timestamp":1734722114000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10360333\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3]]},"references-count":46,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2023.3335949","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,3]]}}}