{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,5]],"date-time":"2026-02-05T10:15:30Z","timestamp":1770286530334,"version":"3.49.0"},"reference-count":56,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2024,8,1]],"date-time":"2024-08-01T00:00:00Z","timestamp":1722470400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2024,8]]},"DOI":"10.1109\/tcsi.2024.3404034","type":"journal-article","created":{"date-parts":[[2024,6,4]],"date-time":"2024-06-04T21:33:48Z","timestamp":1717536828000},"page":"3683-3694","source":"Crossref","is-referenced-by-count":4,"title":["Hybrid Spatial and Temporal Computing Histogrammer in Soft Processor Core of a FPGA Device"],"prefix":"10.1109","volume":"71","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9728-1942","authenticated-orcid":false,"given":"Enrico","family":"Ronconi","sequence":"first","affiliation":[{"name":"Department of Electronics, Information and Bioengineering (DEIB), Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4273-2774","authenticated-orcid":false,"given":"Fabio","family":"Garzetti","sequence":"additional","affiliation":[{"name":"Department of Electronics, Information and Bioengineering (DEIB), Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7635-5308","authenticated-orcid":false,"given":"Nicola","family":"Lusardi","sequence":"additional","affiliation":[{"name":"Department of Electronics, Information and Bioengineering (DEIB), Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9135-2639","authenticated-orcid":false,"given":"Andrea","family":"Costa","sequence":"additional","affiliation":[{"name":"Department of Electronics, Information and Bioengineering (DEIB), Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6084-3953","authenticated-orcid":false,"given":"Angelo","family":"Geraci","sequence":"additional","affiliation":[{"name":"Department of Electronics, Information and Bioengineering (DEIB), Politecnico di Milano, Milan, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1021\/acs.analchem.8b01551"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.7763\/IJCTE.2012.V4.614"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1016\/j.measurement.2018.02.008","article-title":"Detection of power quality event using histogram of oriented gradients and support vector machine","volume":"120","author":"Kapoor","year":"2018","journal-title":"Measurement"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2588555.2612174"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1038\/s42254-019-0062-2"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.trb.2017.11.007"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1287\/opre.2019.1978"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.agwat.2016.12.019"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/cje.2017.09.026"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.jsv.2017.02.046"},{"issue":"2","key":"ref11","first-page":"524","article-title":"An improved local binary patterns histograms techniques for face recognition for real time application","volume":"8","author":"Anand","year":"2019","journal-title":"Int. J. Recent Technol. Eng."},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICBIR.2018.8391187"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2993722"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s11042-018-5647-8"},{"key":"ref15","first-page":"139","article-title":"A new FPGA and programmable SoC based VLSI architecture for histogram generation of grayscale images for image processing applications","volume-title":"Proc. Comput. Sci.","volume":"93","author":"Hazra"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/NSS\/MIC42101.2019.9059842"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.3390\/s17092115"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2017.2666458"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1080\/01691864.2013.839091"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1063\/1.5115349"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3169760"},{"key":"ref22","volume-title":"7 Series FPGAs Memory Resources","year":"2019"},{"key":"ref23","volume-title":"MicroBlazeProcessor Reference Guide","year":"2019"},{"key":"ref24","volume-title":"7 Series FPGAs Data Sheet: Overview","year":"2020"},{"key":"ref25","volume-title":"Digilent Nexys 4","year":"2023"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.57"},{"key":"ref27","article-title":"Fast integral histogram computations on GPU for real-time video analytics","author":"Poostchi","year":"2017","journal-title":"arXiv:1711.01919"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1002\/adom.201801415"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1103\/physrevaccelbeams.23.020401"},{"key":"ref30","first-page":"2632","article-title":"Multichannel end-to-end speech recognition","volume-title":"Proc. Int. Conf. Mach. Learn.","author":"Ochiai"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1088\/1757-899X\/322\/5\/052032"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2956524"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"87","DOI":"10.1016\/j.micpro.2016.11.006","article-title":"High speed FPGA-based data acquisition system","volume":"49","author":"Khedkar","year":"2017","journal-title":"Microprocessors Microsystems"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2019.2908220"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/NSS\/MIC42101.2019.9059671"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9063045"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1016\/j.nima.2018.12.030"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISIE.2014.6864756"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2011.6131111"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1088\/1757-899X\/745\/1\/012044"},{"key":"ref41","volume-title":"7 Series FPGAs Configurable Logic Block","year":"2011"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2013.6531108"},{"key":"ref43","volume-title":"AMBA AXI ACE Protocol Specification","year":"2011"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/NSS\/MIC42677.2020.9507844"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3194265"},{"key":"ref46","volume-title":"AXI Video Direct Memory Access V6.2","year":"2019"},{"key":"ref47","volume-title":"AXI DMA V7.1","year":"2019"},{"key":"ref48","volume-title":"AXI Central Direct Memory Access V4.1","year":"2018"},{"key":"ref49","first-page":"63","article-title":"FPGA implementation of parallel histogram computation","volume-title":"Proc. 2nd HIPEAC Workshop Reconfigurable Comput.","author":"Shahbahrami"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2019.2900541"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3088448"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2023.3322007"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3227462"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/NSS\/MIC42677.2020.9508003"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2022.3198442"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3113033"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8919\/10618913\/10547595.pdf?arnumber=10547595","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,2]],"date-time":"2024-08-02T07:03:13Z","timestamp":1722582193000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10547595\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,8]]},"references-count":56,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2024.3404034","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,8]]}}}