{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:58:25Z","timestamp":1780675105927,"version":"3.54.1"},"reference-count":63,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2024,8,1]],"date-time":"2024-08-01T00:00:00Z","timestamp":1722470400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,8,1]],"date-time":"2024-08-01T00:00:00Z","timestamp":1722470400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,8,1]],"date-time":"2024-08-01T00:00:00Z","timestamp":1722470400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100011688","name":"Electronic Components and Systems for European Leadership Joint Undertaking","doi-asserted-by":"publisher","award":["826655"],"award-info":[{"award-number":["826655"]}],"id":[{"id":"10.13039\/501100011688","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2024,8]]},"DOI":"10.1109\/tcsi.2024.3406522","type":"journal-article","created":{"date-parts":[[2024,6,6]],"date-time":"2024-06-06T17:47:49Z","timestamp":1717696069000},"page":"3538-3549","source":"Crossref","is-referenced-by-count":3,"title":["Toward Efficient System-on-Module for Design-Space Exploration of Analog Spiking Neural Networks"],"prefix":"10.1109","volume":"71","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-2913-1151","authenticated-orcid":false,"given":"Moamen","family":"El-Masry","sequence":"first","affiliation":[{"name":"Infineon Technologies AG, Neubiberg, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Thilo","family":"Werner","sequence":"additional","affiliation":[{"name":"Ferroelectric Memory Company GmbH, Dresden, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Amir","family":"Zjajo","sequence":"additional","affiliation":[{"name":"Innatera Nanosystems B.V., Rijswijk, EX, The Netherlands"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3131-1800","authenticated-orcid":false,"given":"Robert","family":"Weigel","sequence":"additional","affiliation":[{"name":"Institute of Electronics Engineering, Friedrich-Alexander University Erlangen-Nuremberg, Erlangen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050933"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2012.2197858"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/BioCAS.2014.6981816"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2017.2759700"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2014.2379294"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2881432"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2313565"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-91741-8_6"},{"key":"ref9","article-title":"The SpiNNaker 2 processing element architecture for hybrid digital neuromorphic computing","author":"Hoppner","year":"2021","journal-title":"arXiv:2103.08392"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2970709"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2017.01.003"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/cicc.2011.6055293"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/tbcas.2018.2880425"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC48613.2020.9336139"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2021.664208"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2884901"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1126\/science.1254642"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/BIOCAS.2017.8325230"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-33269-2_16"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772783"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS57966.2023.10168582"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/imw52921.2022.9779300"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IMW48823.2020.9108121"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC58585.2023.10257044"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ETFA45728.2021.9613183"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IMS19712.2021.9574994"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC53507.2021.9613939"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3071956"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2018.2848203"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2015.00141"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2456372"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1186\/s11671-020-03299-9"},{"key":"ref34","first-page":"166","article-title":"Self-rectifying bipolar TaOx\/TiO2 RRAM with superior endurance over 1012 cycles for 3D high-density storage-class memory","volume-title":"Proc. Symp. VLSI Technol.","author":"Hsu"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.2200\/s00681ed1v01y201510eet006"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1126\/sciadv.aat4752"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2017.2754383"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.3026667"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1186\/1556-276X-9-526"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796677"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1002\/9783527680870.ch25"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9062985"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2022.959626"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1186\/s11671-022-03722-3"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/imw56887.2023.10145951"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1002\/adma.202305465"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614681"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993573"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265099"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537563"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2011.00073"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1162\/neco.2007.19.10.2581"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2019396"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.3390\/mi12080913"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.829399"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424411"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/irps.2013.6532093"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858403"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417942"},{"key":"ref61","first-page":"108","article-title":"A 250-MHz 256b-I\/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors","volume-title":"Proc. Symp. VLSI Technol.","author":"Noguchi"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062962"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2942267"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8919\/10618913\/10551637.pdf?arnumber=10551637","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,19]],"date-time":"2024-12-19T19:47:13Z","timestamp":1734637633000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10551637\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,8]]},"references-count":63,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2024.3406522","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,8]]}}}