{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T18:05:06Z","timestamp":1772906706086,"version":"3.50.1"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"German Research Foundation (DFG) within the Project PLiM","award":["DR 287\/35-1"],"award-info":[{"award-number":["DR 287\/35-1"]}]},{"name":"German Research Foundation (DFG) within the Project PLiM","award":["DR 287\/35-2"],"award-info":[{"award-number":["DR 287\/35-2"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2024,9]]},"DOI":"10.1109\/tcsi.2024.3424682","type":"journal-article","created":{"date-parts":[[2024,7,16]],"date-time":"2024-07-16T17:50:18Z","timestamp":1721152218000},"page":"4169-4179","source":"Crossref","is-referenced-by-count":7,"title":["<i>veriSIMPLER<\/i>: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing"],"prefix":"10.1109","volume":"71","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7237-5878","authenticated-orcid":false,"given":"Chandan Kumar","family":"Jha","sequence":"first","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-7408-8399","authenticated-orcid":false,"given":"Khushboo","family":"Qayyum","sequence":"additional","affiliation":[{"name":"German Research Centre for Artificial Intelligence (DFKI), Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3334-362X","authenticated-orcid":false,"given":"Kemal","family":"\u00c7a\u011flar Co\u015fkun","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8297-1470","authenticated-orcid":false,"given":"Simranjeet","family":"Singh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3586-8590","authenticated-orcid":false,"given":"Muhammad","family":"Hassan","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6735-3033","authenticated-orcid":false,"given":"Rainer","family":"Leupers","sequence":"additional","affiliation":[{"name":"Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Aachen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3708-5621","authenticated-orcid":false,"given":"Farhad","family":"Merchant","sequence":"additional","affiliation":[{"name":"School of Engineering, Newcastle University, Newcastle upon Tyne, U.K."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9872-1740","authenticated-orcid":false,"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/s41565-020-0655-z"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2016.2583673"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2021.3092533"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240811"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2570248"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3001247"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2022.3222015"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI49217.2020.000-3"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2792474"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2018.10.001"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2931188"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3465371"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203782"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2570120"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474211"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/b105236"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/tetc.2023.3268137"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586324"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3432815"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/40.372360"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3184-2"},{"key":"ref24","first-page":"1","article-title":"CONTRA: Area-constrained technology mapping framework for memristive memory processing unit","volume-title":"Proc. IEEE\/ACM Int. Conf. Comput. Aided Design (ICCAD)","author":"Bhattacharjee"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927095"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DSD57027.2022.00114"},{"key":"ref27","first-page":"19","article-title":"Automated equivalence checking method for majority based in-memory computing on ReRAM crossbars","volume-title":"Proc. 28th Asia South Pacific Design Autom. Conf. (ASP-DAC)","author":"Deb"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1038\/nature08940"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-8931-4"},{"key":"ref30","first-page":"97","article-title":"Yosys\u2014A free verilog synthesis suite","volume-title":"Proc. 21st Austrian Workshop Microelectron. (Austrochip)","author":"Wolf"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78800-3_24"},{"key":"ref32","first-page":"151","article-title":"A neural netlist of 10 combinational benchmark circuits","volume-title":"Proc. IEEE ISCAS Special Session ATPG Fault Simul.","author":"Brglez"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref35","article-title":"IWLS\u201993 benchmark set: Version 4.0","author":"McElvain","year":"1993"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2016.7482461"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-27739-9_1655-1"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/MESIICON55227.2022.10093493"},{"key":"ref39","article-title":"The AIGER and-inverter graph (AIG) format version 20071012","author":"Biere","year":"2007"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref41","first-page":"124","article-title":"Magic: An industrial-strength logic optimization, technology mapping, and formal verification tool","volume-title":"Proc. IWLS","author":"Mishchenko"},{"key":"ref42","article-title":"Applications of SMT solvers to program verification","author":"Bj\u00f8rner","year":"2014"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-95582-7_44"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-34968-4_29"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-72016-2_8"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194643"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3209550"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8919\/10654306\/10599937.pdf?arnumber=10599937","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T04:01:49Z","timestamp":1725163309000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10599937\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9]]},"references-count":47,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2024.3424682","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,9]]}}}