{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T22:51:22Z","timestamp":1776725482540,"version":"3.51.2"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2024,10,1]],"date-time":"2024-10-01T00:00:00Z","timestamp":1727740800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,10,1]],"date-time":"2024-10-01T00:00:00Z","timestamp":1727740800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,10,1]],"date-time":"2024-10-01T00:00:00Z","timestamp":1727740800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,10,1]],"date-time":"2024-10-01T00:00:00Z","timestamp":1727740800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100020844","name":"Interuniversity Microelectronics Centre","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100020844","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100006192","name":"Advanced Scientific Computing Research (ASCR) Program of U.S. Department of Energy","doi-asserted-by":"publisher","award":["DESC0022881"],"award-info":[{"award-number":["DESC0022881"]}],"id":[{"id":"10.13039\/100006192","id-type":"DOI","asserted-by":"publisher"}]},{"name":"National Science Foundation","award":["CCF-2219753"],"award-info":[{"award-number":["CCF-2219753"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2024,10]]},"DOI":"10.1109\/tcsi.2024.3438164","type":"journal-article","created":{"date-parts":[[2024,8,19]],"date-time":"2024-08-19T17:39:59Z","timestamp":1724089199000},"page":"4597-4610","source":"Crossref","is-referenced-by-count":4,"title":["Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus"],"prefix":"10.1109","volume":"71","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0926-2838","authenticated-orcid":false,"given":"Zhenlin","family":"Pei","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, The University of Texas at Arlington, Arlington, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2305-4258","authenticated-orcid":false,"given":"Hsiao-Hsuan","family":"Liu","sequence":"additional","affiliation":[{"name":"imec, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6084-9810","authenticated-orcid":false,"given":"Mahta","family":"Mayahinia","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8829-5610","authenticated-orcid":false,"given":"Mehdi B.","family":"Tahoori","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3599-8515","authenticated-orcid":false,"given":"Francky","family":"Catthoor","sequence":"additional","affiliation":[{"name":"imec, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3545-3424","authenticated-orcid":false,"given":"Zsolt","family":"T\u0151kei","sequence":"additional","affiliation":[{"name":"imec, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3598-8798","authenticated-orcid":false,"given":"Dawit Burusie","family":"Abdi","sequence":"additional","affiliation":[{"name":"imec, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-2558-7504","authenticated-orcid":false,"given":"James","family":"Myers","sequence":"additional","affiliation":[{"name":"imec, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9161-1728","authenticated-orcid":false,"given":"Chenyun","family":"Pan","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, The University of Texas at Arlington, Arlington, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9063030"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2020.3030062"},{"key":"ref3","article-title":"Design of SRAM for CMOS 32nm","author":"Hamouche","year":"2011"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ted.2022.3225512"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/iedm.2018.8614535"},{"key":"ref6","article-title":"Circuit delay and power benchmark of graphene against Cu interconnects","author":"Contino"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/tnano.2022.3157952"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9591-6"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731673"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/NAS51552.2021.9605440"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3210070"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2021.3056674"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3202254"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2023.3305322"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3583781.3590311"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3185768.3185771"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2021.3074251"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3490391"},{"key":"ref20","volume-title":"Spectre","year":"2023"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3401025.3401742"},{"key":"ref22","volume-title":"Virtuoso","year":"2023"},{"key":"ref23","volume-title":"QuickCap","year":"2023"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2023.3235701"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1117\/12.2657524"},{"key":"ref26","article-title":"CACTI 5.1","author":"Thoziyoor","year":"2008"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3085572"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED57927.2023.10129316"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/j.ssc.2008.02.024"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/IITC47697.2020.9515595"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1021\/nn405834b"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/edtm.2019.8731225"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/j.carbon.2021.07.070"},{"key":"ref34","article-title":"Graphene-ruthenium hybrid interconnects","author":"Achra"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/iitc-amc.2016.7507650"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/led.2013.2291783"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1016\/j.carbon.2019.04.101"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139164313"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2010.2071395"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/tmtt.2019.2955123"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/iedm.2017.8268389"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/IITC-AMC.2017.7968949"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1021\/acs.nanolett.6b04516"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2409875"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.3390\/c4030049"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2016.0376"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.2307\/20637317"},{"key":"ref48","article-title":"CACTI 6.0: A tool to model large caches","author":"Muralimanohar","year":"2009"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1117\/12.2583395"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/8919\/10702478\/10638740-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8919\/10702478\/10638740.pdf?arnumber=10638740","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,20]],"date-time":"2024-12-20T19:15:44Z","timestamp":1734722144000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10638740\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10]]},"references-count":49,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2024.3438164","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,10]]}}}