{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T16:48:38Z","timestamp":1764175718096,"version":"3.40.3"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"German Research Foundation within the Project PLiM","award":["DR 287\/35-1","DR 287\/35-2"],"award-info":[{"award-number":["DR 287\/35-1","DR 287\/35-2"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2025,4]]},"DOI":"10.1109\/tcsi.2024.3509013","type":"journal-article","created":{"date-parts":[[2024,12,11]],"date-time":"2024-12-11T03:57:06Z","timestamp":1733889426000},"page":"1718-1730","source":"Crossref","is-referenced-by-count":1,"title":["<i>Correct and Verify<\/i>\u2014CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders With Correct Carry Bits"],"prefix":"10.1109","volume":"72","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7237-5878","authenticated-orcid":false,"given":"Chandan Kumar","family":"Jha","sequence":"first","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-7408-8399","authenticated-orcid":false,"given":"Khushboo","family":"Qayyum","sequence":"additional","affiliation":[{"name":"German Research Centre for Artificial Intelligence (DFKI), Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3586-8590","authenticated-orcid":false,"given":"Muhammad","family":"Hassan","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9872-1740","authenticated-orcid":false,"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/b107399"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0817-5"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/b105236"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/c2013-0-18672-2"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675141"},{"volume-title":"Equivalence Checking of Digital Circuits: Fundamentals, Principles, Methods","year":"2007","author":"Molitor","key":"ref6"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3083682"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-21514-8_33"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116296"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.3006451"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH48897.2020.00025"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.2999613"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2023.102084"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105401"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2893356"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.3020792"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-024-06356-7"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2910137"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3268275"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISDCS58735.2023.10153565"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2018.8649985"},{"key":"ref22","first-page":"1449","article-title":"A new approximate adder with low relative error and correct sign calculation","volume-title":"Proc. Design, Autom. Test Eur. Conf. Exhib.","author":"Hu"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS47518.2019.8953155"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2958605"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203807"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3197229"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/AQTR55203.2022.9801944"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID60093.2024.00102"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.3012194"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993675"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2772854"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"volume-title":"CUDD: CU decision diagram package release 2.4. 2","year":"2009","author":"Somenzi","key":"ref33"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320087"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3388256"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2022.3222015"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS52668.2021.9417052"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/MESIICON55227.2022.10093493"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3218021"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2023.3287631"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/DSD57027.2022.00107"},{"key":"ref42","first-page":"1","article-title":"Yosys\u2014A free verilog synthesis suite","volume-title":"Proc. 21st Austrian Workshop Microelectron. (Austrochip)","volume":"97","author":"Wolf"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8919\/10944800\/10790927.pdf?arnumber=10790927","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,29]],"date-time":"2025-03-29T09:36:44Z","timestamp":1743241004000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10790927\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4]]},"references-count":42,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2024.3509013","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2025,4]]}}}