{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T18:20:44Z","timestamp":1775067644196,"version":"3.50.1"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002322","name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior\u2014Brazil (CAPES) under Finance Code 001","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"publisher"}]},{"name":"FAPERGS\u2014TECHFUTURO Semiconductors Program","award":["23\/25551-0002204-4"],"award-info":[{"award-number":["23\/25551-0002204-4"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2025,4]]},"DOI":"10.1109\/tcsi.2024.3511383","type":"journal-article","created":{"date-parts":[[2024,12,19]],"date-time":"2024-12-19T14:47:12Z","timestamp":1734619632000},"page":"1679-1692","source":"Crossref","is-referenced-by-count":4,"title":["FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders"],"prefix":"10.1109","volume":"72","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9582-9011","authenticated-orcid":false,"given":"Morgana Macedo Azevedo da","family":"Rosa","sequence":"first","affiliation":[{"name":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"}]},{"given":"Leonardo","family":"Antonietti","sequence":"additional","affiliation":[{"name":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"}]},{"given":"Rodrigo","family":"Lopes","sequence":"additional","affiliation":[{"name":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"}]},{"given":"Eloisa","family":"Barros","sequence":"additional","affiliation":[{"name":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0521-5898","authenticated-orcid":false,"given":"Eduardo Antonio Ce\u015bar da","family":"Costa","sequence":"additional","affiliation":[{"name":"Department of Graduate Program on Electronic Engineering and Computing, Universidade Católica de Pelotas (UCPel), Pelotas, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9493-7272","authenticated-orcid":false,"given":"Rafael","family":"Soares","sequence":"additional","affiliation":[{"name":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2023.3331675"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/icce-asia49877.2020.9277304"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.3390\/electronics8111212"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/isocc50952.2020.9332971"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2017.8292078"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS202256217.2022.9970839"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2027626"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3218021"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS58634.2023.10382842"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691096"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744778"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228509"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176685"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/PRIME.2015.7251090"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2564699"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020591"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/tencon.2018.8650127"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MIEL.2019.8889605"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2217962"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9030471"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS51387.2021.9687757"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3047651"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2822278"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1587\/elex.17.20200218"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2015.7180603"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2020.106761"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2021.153825"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS49266.2020.9294854"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2021.3120237"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2856757"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2605382"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218533"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED57927.2023.10129364"},{"key":"ref34","first-page":"1","article-title":"AxHLS: Design space exploration and high-level synthesis of approximate accelerators using approximate functional units and analytical models","volume-title":"Proc. IEEE\/ACM Int. Conf. Comput. Aided Design (ICCAD)","author":"Castro-God\u00ednez"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3240897"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2981395"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3252483"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3346289"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3087858"},{"key":"ref40","first-page":"1","article-title":"The OpenROAD project: Unleashing hardware innovation","volume-title":"Proc. GOMAC","author":"Kahng"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2019.2945763"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS48785.2022.9937770"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8919\/10944800\/10807460.pdf?arnumber=10807460","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T19:54:06Z","timestamp":1774641246000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10807460\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4]]},"references-count":42,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2024.3511383","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,4]]}}}