{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,30]],"date-time":"2026-07-30T14:18:58Z","timestamp":1785421138106,"version":"3.56.0"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100008628","name":"Ministry of Electronics and Information Technology, Government of India","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100008628","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2025,6]]},"DOI":"10.1109\/tcsi.2025.3555891","type":"journal-article","created":{"date-parts":[[2025,4,14]],"date-time":"2025-04-14T13:42:12Z","timestamp":1744638132000},"page":"2818-2831","source":"Crossref","is-referenced-by-count":5,"title":["Inductive GNN-Based Methodology for Accurate and Fast Average Power Estimation of Synthesized ASIC Designs From RTL Simulation Bypassing Gate-Level Simulation"],"prefix":"10.1109","volume":"72","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7819-551X","authenticated-orcid":false,"given":"M. B.","family":"Rakesh","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Indian Institute of Technology at Hyderabad, Hyderabad, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pabitra","family":"Das","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Indian Institute of Technology at Hyderabad, Hyderabad, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"K. R. Sai","family":"Pranav","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Indian Institute of Technology at Hyderabad, Hyderabad, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5636-0676","authenticated-orcid":false,"given":"Amit","family":"Acharyya","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Indian Institute of Technology at Hyderabad, Hyderabad, India"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218643"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2002.1187270"},{"key":"ref3","first-page":"1","article-title":"Inductive representation learning on large graphs","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Hamilton"},{"key":"ref4","first-page":"1","article-title":"PRIMAL: Power inference using machine learning","volume-title":"Proc. 56th ACM\/IEEE Design Autom. Conf. (DAC)","author":"Zhou"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS202256217.2022.9970951"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3003276"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1994.204066"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.205010"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.681258"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.1996.547490"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3451179"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.831478"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/348019.348081"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2003.1183173"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059105"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.48550\/ARXIV.1609.02907"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3112826"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3093420"},{"key":"ref19","article-title":"Deep graph library: A graph-centric, highly-performant package for graph neural networks","author":"Wang","year":"2019","journal-title":"arXiv:1909.01315"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2020.2978386"},{"key":"ref21","volume-title":"Digital Integrated Circuits: A Design Perspective","volume":"2","author":"Rabaey","year":"2002"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/43.137524"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.25080\/tcwv9851"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3168344"},{"key":"ref25","volume-title":"Fixed Point Math Library for Verilog and Floating Point Adder and Multiplier","year":"2019"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/54.785838"},{"key":"ref27","article-title":"The EPFL combinational benchmark suite","volume-title":"Proc. 24th Int. Workshop Log. Synth. (IWLS)","author":"Amar\u00fa"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.5555\/3454287.3455008"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2970724"},{"key":"ref30","first-page":"1","article-title":"Opportunities for RTL and gate level simulation using GPUs","volume-title":"Proc. 39th Int. Conf. Comput.-Aided Design","author":"Zhang"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530497"},{"key":"ref32","article-title":"DeepSeq: Deep sequential circuit learning","author":"Khan","year":"2023","journal-title":"arXiv:2302.13608"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2023.3262952"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2022.3141665"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.3390\/ai3010011"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2022.06.097"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3583780.3614955"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2939720"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD52597.2021.9531070"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.2200\/S01045ED1V01Y202009AIM046"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8919\/11018065\/10964401.pdf?arnumber=10964401","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T20:14:01Z","timestamp":1781813641000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10964401\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6]]},"references-count":40,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2025.3555891","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,6]]}}}