{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T18:03:24Z","timestamp":1761674604456,"version":"build-2065373602"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62176025","62301066","U21B2045","62206012"],"award-info":[{"award-number":["62176025","62301066","U21B2045","62206012"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"publisher","award":["2023RC72"],"award-info":[{"award-number":["2023RC72"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2025,11]]},"DOI":"10.1109\/tcsi.2025.3570805","type":"journal-article","created":{"date-parts":[[2025,5,26]],"date-time":"2025-05-26T14:10:31Z","timestamp":1748268631000},"page":"7016-7029","source":"Crossref","is-referenced-by-count":0,"title":["DrlGoFPGA: FPGA Global Placement Considering Input-Output Buffer Based on Deep Reinforcement Learning and Gradient Optimization"],"prefix":"10.1109","volume":"72","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1366-1110","authenticated-orcid":false,"given":"Kang","family":"Yang","sequence":"first","affiliation":[{"name":"School of Integrated Circuit, Beijing University of Posts and Telecommunications, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1581-3536","authenticated-orcid":false,"given":"Jianwang","family":"Zhai","sequence":"additional","affiliation":[{"name":"School of Integrated Circuit, Beijing University of Posts and Telecommunications, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8486-6255","authenticated-orcid":false,"given":"Liuyu","family":"Xiang","sequence":"additional","affiliation":[{"name":"School of Artificial Intelligence, Beijing University of Posts and Telecommunications, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-2194-5448","authenticated-orcid":false,"given":"Zixi","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Artificial Intelligence, Beijing University of Posts and Telecommunications, Beijing, China"}]},{"given":"Dan","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Artificial Intelligence, Beijing University of Posts and Telecommunications, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-9218-3271","authenticated-orcid":false,"given":"Yida","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Artificial Intelligence, Beijing University of Posts and Telecommunications, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0502-8523","authenticated-orcid":false,"given":"Kang","family":"Zhao","sequence":"additional","affiliation":[{"name":"School of Integrated Circuit, Beijing University of Posts and Telecommunications, Beijing, China"}]},{"given":"Ming","family":"Lei","sequence":"additional","affiliation":[{"name":"School of Integrated Circuit, Beijing University of Posts and Telecommunications, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3433-8435","authenticated-orcid":false,"given":"Zhaofeng","family":"He","sequence":"additional","affiliation":[{"name":"School of Artificial Intelligence, Beijing University of Posts and Telecommunications, Beijing, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s40031-020-00508-y"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC52403.2022.9712562"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942075"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON58565.2023.10396248"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00070"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2019.8916251"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3109863"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD48534.2019.9142079"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530566"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3380446.3430618"},{"key":"ref11","article-title":"Chip placement with deep reinforcement learning","author":"Mirhoseini","year":"2020","journal-title":"arXiv:2004.10746"},{"key":"ref12","first-page":"16508","article-title":"On joint learning for solving placement and routing in chip design","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Cheng"},{"key":"ref13","first-page":"24019","article-title":"MaskPlace: Fast chip placement via reinforced visual representation learning","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Lai"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2897650"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-023-48981-x"},{"volume-title":"UltraScale Architecture and Product Overview","year":"2024","key":"ref16"},{"key":"ref17","first-page":"664","article-title":"TSV-aware analytical placement for 3D IC designs","volume-title":"Proc. 48th ACM\/EDAC\/IEEE Design Autom. Conf. (DAC)","author":"Hsu"},{"key":"ref18","first-page":"1","article-title":"PyTorch: An imperative style, high-performance deep learning library","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Paszke"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317803"},{"key":"ref20","article-title":"Exploration by random network distillation","author":"Burda","year":"2018","journal-title":"arXiv:1810.12894"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3071507"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1038\/s44172-023-00127-7"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2012.08.003"},{"key":"ref24","article-title":"Proximal policy optimization algorithms","author":"Schulman","year":"2017","journal-title":"arXiv:1707.06347"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.48550\/ARXIV.1609.02907"},{"article-title":"Automatic differentia-tion in Pytorch","volume-title":"Proc. 31st Conf. Neural Inf. Process. Syst. (NIPS)","author":"Paszke","key":"ref26"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2872334.2886419"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3036669.3038241"},{"key":"ref29","article-title":"Adam: A method for stochastic optimization","author":"Kingma","year":"2014","journal-title":"arXiv:1412.6980"},{"key":"ref30","article-title":"DREAMPlaceFPGA-MP: An open-source GPU-accelerated macro placer for modern FPGAs with cascade shapes and region constraints","author":"Xiong","year":"2023","journal-title":"arXiv:2311.08582"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISEDA62518.2024.10617535"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD58807.2023.10299868"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.48550\/ARXIV.1706.03762"},{"key":"ref34","article-title":"Long short-term memory based recurrent neural network architectures for large vocabulary speech recognition","author":"Sak","year":"2014","journal-title":"arXiv:1402.1128"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8919\/11217317\/11015632.pdf?arnumber=11015632","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T17:40:34Z","timestamp":1761673234000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11015632\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11]]},"references-count":34,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2025.3570805","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2025,11]]}}}