{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T00:28:24Z","timestamp":1787012904412,"version":"3.56.0"},"reference-count":48,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:00:00Z","timestamp":1775001600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:00:00Z","timestamp":1775001600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:00:00Z","timestamp":1775001600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["12127808"],"award-info":[{"award-number":["12127808"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["12141503"],"award-info":[{"award-number":["12141503"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2026,4]]},"DOI":"10.1109\/tcsi.2025.3620579","type":"journal-article","created":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T17:40:41Z","timestamp":1761673241000},"page":"2397-2410","source":"Crossref","is-referenced-by-count":3,"title":["A 1-GS\/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS"],"prefix":"10.1109","volume":"73","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2631-971X","authenticated-orcid":false,"given":"Peng","family":"Wang","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-2703-9938","authenticated-orcid":false,"given":"Nan","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7341-7240","authenticated-orcid":false,"given":"Fule","family":"Li","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6567-0759","authenticated-orcid":false,"given":"Zhihua","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3471915"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2886327"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2384025"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3290119"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3133829"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870368"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662524"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3169508"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3307435"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2009.4977320"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067258"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217865"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2453332"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3344461"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/a-sscc60305.2024.10848587"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2014.6757399"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC56115.2022.9980717"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3408468"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904536"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/vlsic.2014.6858451"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3222162"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631448"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2169854"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.816921"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.856291"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310274"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2010.5433830"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2082850"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2641259"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2013.6487818"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454299"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2019.8902706"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/esscirc.2016.7598330"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2785349"},{"key":"ref37","first-page":"C268","article-title":"A 2.1 mW 11b 410 MS\/s dynamic pipelined SAR ADC with background calibration in 28 nm digital CMOS","volume-title":"Proc. Symp. VLSI Circuits","author":"Verbruggen"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2025.3526593"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1049\/el:20000501"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.23919\/vlsic.2017.8008507"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3023882"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2768404"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/CICC60959.2024.10529030"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234320"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2961149"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904526"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2024.3355739"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC59616.2023.10268748"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8919\/11458063\/11219406.pdf?arnumber=11219406","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,3]],"date-time":"2026-04-03T19:57:15Z","timestamp":1775246235000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11219406\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4]]},"references-count":48,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2025.3620579","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,4]]}}}