{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,28]],"date-time":"2025-09-28T06:53:55Z","timestamp":1759042435329},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2009,5,1]],"date-time":"2009-05-01T00:00:00Z","timestamp":1241136000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2009,5]]},"DOI":"10.1109\/tcsii.2009.2019165","type":"journal-article","created":{"date-parts":[[2009,4,15]],"date-time":"2009-04-15T16:02:35Z","timestamp":1239811355000},"page":"364-368","source":"Crossref","is-referenced-by-count":30,"title":["Utilizing Process Variations for Reference Generation in a Flash ADC"],"prefix":"10.1109","volume":"56","author":[{"given":"T.","family":"Sundstrom","sequence":"first","affiliation":[]},{"given":"A.","family":"Alvandpour","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.921596"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.545804"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1997.608492"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1865","DOI":"10.1109\/JSSC.2007.903053","article-title":"a 4-gs\/s 4-bit flash adc in 0.18- cmos","volume":"42","author":"park","year":"2007","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2007.4286149"},{"key":"ref15","year":"2000","journal-title":"IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001936"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405746"},{"key":"ref4","year":"0","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2005.1568738"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.987096"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346637"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2002548"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.852198"},{"key":"ref2","first-page":"699","author":"bhunia","year":"2007","journal-title":"IEEE VLSI Des"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.917991"}],"container-title":["IEEE Transactions on Circuits and Systems II: Express Briefs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8920\/4939458\/04814560.pdf?arnumber=4814560","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:51:35Z","timestamp":1633909895000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4814560\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,5]]},"references-count":17,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2009.2019165","relation":{},"ISSN":["1549-7747","1558-3791"],"issn-type":[{"value":"1549-7747","type":"print"},{"value":"1558-3791","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,5]]}}}